FAN5069_08 Datasheet, PDF (15/22 Pages) Fairchild Semiconductor – PWM and LDO Controller Combo

P_GATE is determined by the following equation:
P_Gate = Q_G × V_CC × F_SW
(EQ. 14)
where Q_G is the total gate charge to reach V_CC.
Low-Side Losses
Q2 switches on or off with its parallel schottky diode
simultaneously conducting, so the V_DS ≈ 0.5V. Since
P_SW is proportional to V_DS, Q2's switching losses are
negligible and Q2 is selected based on R_DS(ON) alone.
Conduction losses for Q2 are given by the equation:
P_COND = (1 – D) × I_{O2 UT} × R_DS(ON)
(EQ. 15)
where R_DS(ON) is the R_DS(ON) of the MOSFET at the
highest operating junction temperature and D=V_OUT/V_IN
is the minimum duty cycle for the converter.
Since D_MIN < 20% for portable computers, (1-D) ≈ 1 pro-
duces a conservative result, simplifying the calculation.
The maximum power dissipation (P_D(MAX)) is a function
of the maximum allowable die temperature of the low-
side MOSFET, the θ_JA, and the maximum allowable
ambient temperature rise. P_D(MAX) is calculated using
the following equation:
P_D(MAX) = ^T----^J---⁽--^M----^A----^X---⁾-_θ--–-_J---_A-^T----^A---⁽--^M----^A----^X---⁾
(EQ. 16)
θ_JA depends primarily on the amount of PCB area
devoted to heat sinking.
Selection of MOSFET Snubber Circuit
The Switch node (SW) ringing is caused by fast switch-
ing transitions due to the energy stored in the parasitic
elements. This ringing on the SW node couples to other
circuits around the converter if they are not handled
properly. To dampen this ringing, an R-C snubber is con-
nected across the SW node and the source of the low-
side MOSFET.
R-C components for the snubber are selected as follows:
a) Measure the SW node ringing frequency (F_ring) with a
low capacitance scope probe.
b) Connect a capacitor (C_SNUB) from SW node to GND
so that it reduces this ringing by half.
c) Place a resistor (R_SNUB) in series with this capacitor.
R_SNUB is calculated using the following equation:
R_SNUB = -_π----_×-----_F----_r--_i-_n---_g--²--_×-----_C-----_S---_N----_U----_B-
(EQ. 17)
d) Calculate the power dissipated in the snubber resistor
as shown in the following equation:
P_R(SNUB) = C_SNUB × V_I2N(MAX) × F_SW
(EQ. 18)
where, V_IN(MAX) is the maximum input voltage and FSW
is the converter switching frequency.
The snubber resistor chosen should be de-rated to han-
dle the worst-case power dissipation. Do not use wire-
wound resistors for R_SNUB.
Loop Compensation
Typically, the closed loop crossover frequency (F_cross),
where the overall gain is unity, should be selected to
achieve optimal transient and steady-state response to
disturbances in line and load conditions. It is recom-
mended to keep F_cross below fifth of the switching fre-
quency of the converter. Higher phase margin tends to
have a more stable system with more sluggish response
to load transients. Optimum phase margin is about 60°, a
good compromise between steady state and transient
responses. A typical design should address variations
over a wide range of load conditions and over a large
sample of devices.
V_IN
R_RAMP
Ramp
Generator
Current
Sense
Amplifier
Summing
Σ
Amplifier
PWM
&
DRIVER
V_IN
Q1
L
R_DC
C
Q2
R_ES
V_OUT
R_L
C2
C1
R2
Reference
R_BIAS
C3 _R3
R1
Figure 24. Closed-Loop System with Type-3 Network
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
15
www.fairchildsemi.com