FAN5069_08 Datasheet, PDF (12/22 Pages) Fairchild Semiconductor – PWM and LDO Controller Combo

ture is disabled during the start-up until the voltage on
the SS capacitor crosses 1.2V.
To achieve current limit, the FAN5069 monitors the
inductor current during the OFF time by monitoring and
holding the voltage across the lower MOSFET. The volt-
age across the lower MOSFET is sensed between the
PGND and the SW pins.
The output of the summing amplifier is a function of the
inductor current, R_{DS_ON} of the bottom FET and the gain
of the current sense amplifier. With the R_{DS_ON} method
of current sensing, the current limit can vary widely from
unit to unit. R_{DS_ON} not only varies from unit to unit, but
also has a typical junction temperature coefficient of
about 0.4%/°C (consult the MOSFET datasheet for
actual values). The set point of the actual current limit
decreases in proportion to increase in MOSFET die tem-
perature. A factor of 1.6 in the current limit set point typi-
cally compensates for all MOSFET R_{DS_ON} variations,
assuming the MOSFET's heat sinking keeps its operat-
ing die temperature below 125°C.
For more accurate current limit setting, use resistor
sensing. In a resistor sensing scheme, an appropriate
current sense resistor is connected between the source
terminal of the bottom MOSFET and PGND.
Set the current limit by choosing R_ILIM as follows:
R_ILIM =
128
+
K_-----1_-----•_----I_{--M----A----X----1}•_---.--R4_{---3-D----S---O----N-----}•_----1_----0_---³_-
+
⎛
⎜
⎝
⎛
⎝
1
–
V^-1---.-i^-8-n^{-⎠⎞}
•
V_-----o_---F-u_---St_---•_-W----3_--•-3_---R.--3_--R-2_---A--•_--M---1_-P--0_---¹_---¹_-
(EQ. 5)
where R_ILIM is in KΩ.
I_MAX is the maximum load current.
K1 is a constant to accommodate for the variation of
MOSFET R_DS(ON) (typically 1.6).
With K1 = 1.6, I_MAX = 20A, R_DS(ON) = 7mΩ, V_IN = 24V,
V_OUT = 1.5V, F_SW = 300 KHz, R_RAMP = 400 KΩ, R_ILIM
calculates to be 323.17KΩ.
Auto Restart (PWM)
The FAN5069 supports two modes of response when the
internal fault latch is set. The user can configure it to
keep the power supply latched in the OFF state OR in
the Auto Restart mode. When the EN pin is tied to V_CC,
the power supply is latched OFF. When the EN pin is ter-
minated with a 100nF to GND, the power supply is in
Auto Restart mode. The table below describes the rela-
tionship between PWM restart and setting on EN pin. Do
not leave the EN pin open without any capacitor.
EN Pin
Pull to GND
V_CC
Cap to GND
PWM/Restart
OFF
No restart after fault
Restart after TDELAY (Sec.) =
0.85 x C where C is in μF
The fault latch can also be reset by recycling the V_CC to
the controller.
Under Voltage Protection (PWM)
The PWM converter output is monitored constantly for
under voltage at the FB pin. If the voltage on the FB pin
stays lower than 75% of internal Vref for 16 clock cycles,
the fault latch is set and the converter shuts down. This
shutdown feature is disabled during startup until the volt-
age on the SS capacitor reaches 1.2V.
Over Voltage Protection (PWM)
The PWM converter output voltage is monitored con-
stantly at the FB pin for over voltage. If the voltage on the
FB pin stays higher than 115% of internal V_REF for two
clock cycles, the controller turns OFF the upper MOS-
FET and turns ON the lower MOSFET. This crowbar
action stops when the voltage on the FB pin reaches
0.4V to prevent the output voltage from becoming nega-
tive. This over-voltage protection (OVP) feature is active
as soon as the voltage on the EN pin becomes high.
Turning ON the low-side MOSFETs on an OVP condition
pulls down the output, resulting in a reverse current,
which starts to build up in the inductor. If the output over-
voltage is due to failure of the high-side MOSFET, this
crowbar action pulls down the input supply or blows its
fuse, protecting the system, which is very critical.
During soft-start, if the output overshoots beyond 115%
of V_REF, the output voltage is brought down by the low-
side MOSFET until the voltage on the FB pin goes below
0.4V. The fault latch is NOT set until the voltage on the
SS pin reaches 1.2V. Once the fault latch is set, the con-
verter shuts down.
115% Vref
FB
0.4V
ILIM
UV
OV
Delay
2 Clks
V_SS>1.2V _EN
S
Q
R
S
Fault
Q Latch
R
LS Drive
Figure 21. Over-Voltage Protection
Thermal Fault Protection
The FAN5069 features thermal protection where the IC
temperature is monitored. When the IC junction temper-
ature exceeds +160°C, the controller shuts down and
when the junction temperature gets down to +125°C, the
converter restarts.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
12
www.fairchildsemi.com