FAN5069_08 Datasheet, PDF (13/22 Pages) Fairchild Semiconductor – PWM and LDO Controller Combo

LDO Section
The LDO controller is designed to provide ultra low volt-
ages, as low as 0.8V for GTL-type loads. The regulating
loop employs a very fast response feedback loop and
small capacitors can be used to keep track of the chang-
ing output voltage during transients. For stable opera-
tion, the minimum capacitance on the output needs to be
100µF and the typical ESR needs to be around 100mΩ.
The maximum voltage at the gate drive for the MOSFET
can reach close to 0.5V below the V_CC of the controller.
For example, for a 1.2V output, the minimum enhance-
ment voltage required with 4.75V on V_CC is 3.05V
(4.75V-0.5V-1.2V = 3.05V). The drop-out voltage for the
LDO is dependent on the load current and the MOSFET
chosen. It is recommended to use low enhancement
voltage MOSFETs for the LDO. In applications where
LDO is not needed, pull up the FBLDO pin (Pin #1)
higher than 1V to disable the LDO.
The soft-start on the LDO output (ramp) is controlled by
the capacitor on the SS pin to GND. The LDO output is
enabled only when the voltage on the SS pin reaches
2.2V. Refer to Figure 9 for start-up waveform.
Design Section
General Design Guidelines
Establishing the input voltage range and maximum cur-
rent loading on the converter before choosing the switch-
ing frequency and the inductor ripple current is highly
recommended. There are design trade-offs in choosing
an optimum switching frequency and the ripple current.
The input voltage range should accommodate the worst-
case input voltage with which the converter may ever
operate. This voltage needs to account for the cable drop
encountered from the source to the converter. Typically,
the converter efficiency tends to be higher at lower input
voltage conditions.
When selecting maximum loading conditions, consider
the transient and steady-state (continuous) loading sep-
arately. The transient loading affects the selection of the
inductor and the output capacitors. Steady state loading
affects the selection of MOSFETs, input capacitors, and
other critical heat-generating components.
The selection of switching frequency is challenging.
While higher switching frequency results in smaller com-
ponents, it also results in lower efficiency. Ideal selection
of switching frequency takes into account the maximum
operating voltage. The MOSFET switching losses are
directly proportional to F_SW and the square function of
the input voltage.
When selecting the inductor, consider the minimum and
maximum load conditions. Lower inductor values pro-
duce better transient response, but result in higher ripple
and lower efficiency due to high RMS currents. Optimum
minimum inductance value enables the converter to
operate at the boundary of continuous and discontinuous
conduction modes.
Setting the Output Voltage (PWM)
The internal reference for the PWM controller is at 0.8V.
The output voltage of the PWM regulator can be set in
the range of 0.8V to 90% of its power input by an exter-
nal resistor divider. The output is divided down by an
external voltage divider to the FB pin (for example, R1
and R_BIAS as in Figure 24). The output voltage is given
by the following equation:
V_OUT
=
0.8V
×
⎛
⎝
1
+
R^-----R_B^----_I^1-_A^----_S^{-⎠⎞}
(EQ. 6)
To minimize noise pickup on this node, keep the resistor
to GND (R_BIAS) below 10KΩ.
Inductor Selection (PWM)
When the ripple current, switching frequency of the con-
verter, and the input-output voltages are established,
select the inductor using the following equation:
L_MIN = ^⎝⎛---^V--_I--_RO----_iU-_p---_pT---_l-_e-–---_×-^V------V---_F^O------^I--_SU-^N------_WT^-----2---^⎠⎞-
(EQ. 7)
where I_Ripple is the ripple current.
This number typically varies between 20% to 50% of the
maximum steady-state load on the converter.
When selecting an inductor from the vendors, select the
inductance value which is close to the value calculated at
the rated current (including half the ripple current).
Input Capacitor Selection (PWM)
The input capacitors must have an adequate RMS cur-
rent rating to withstand the temperature rise caused by
the internal power dissipation. The combined RMS cur-
rent rating for the input capacitor should be greater than
the value calculated using the following equation:
⎛
I_INPUT(RMS)
=
I_LOAD(MAX)
×
⎜
⎝
V_{---V--O---I-UN---T--}
–
⎛
⎝
V_{---V--O--I--UN---T--⎠⎞}
2_⎞
⎟
⎠
(EQ.
8)
Common capacitor types used for such application
include aluminum, ceramic, POS CAP, and OSCON.
Output Capacitor Selection (PWM)
The output capacitors chosen must have low enough
ESR to meet the output ripple and load transient require-
ments. The ESR of the output capacitor should be lower
than both of the values calculated below to satisfy both
the transient loading and steady-state ripple conditions
as given by the following equation:
ESR ≤ _Δ-----_I-_L---^V_O----^SA----^TD---^E-₍-_M-^P----_A---_X----₎ and ESR ≤ -^V-_I--_R-^R--_i-ⁱ-_p-^p--_p-^p--_l-^le-^e-
(EQ. 9)
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
13
www.fairchildsemi.com