FAN5069_08 Datasheet, PDF (14/22 Pages) Fairchild Semiconductor – PWM and LDO Controller Combo

In the case of aluminum and polymer based capacitors,
the output capacitance is typically higher than normally
required to meet these requirements. While selecting the
ceramic capacitors for the output; although lower ESR
can be achieved easily, higher capacitance values are
required to meet the V_OUT(MIN) restrictions during a load
transient. From the stability point of view, the zero
caused by the ESR of the output capacitor plays an
important role in the stability of the converter.
Output Capacitor Selection (LDO)
For stable operation, the minimum capacitance of 100µF
with ESR around 100mΩ is recommended. For other val-
ues, contact the factory.
Power MOSFET Selection (PWM)
The FAN5069 is capable of driving N-Channel MOSFETs
as circuit switch elements. For better performance,
MOSFET selection must address these key parameters:
■ The maximum Drain-to-Source Voltage (V_DS) should
be at least 25% higher than worst-case input voltage.
■ The MOSFETs should have low Q_G, Q_GD, and Q_GS.
■ The R_{DS_ON} of the MOSFETs should be as low as possible.
In typical applications for a buck converter, the duty
cycles are lower than 20%. To optimize the selection of
MOSFETs for both the high-side and low-side, follow dif-
ferent selection criteria. Select the high-side MOSFET to
minimize the switching losses and the low-side MOSFET
to minimize the conduction losses due to the channel
and the body diode losses. Note that the gate drive
losses also affect the temperature rise on the controller.
For loss calculation, refer to Fairchild's Application Note
AN-6005 and the associated spreadsheet.
High-Side Losses
Losses in the MOSFET can be understood by following
the switching interval of the MOSFET in Figure 22. MOS-
FET gate drive equivalent circuit is shown in Figure 23.
V_DS
C_ISS
C _GD
C_ISS
I_D
V_SP
V_TH
V_GS
Q_GS
Q_GD
Q_G(SW)
t1
t2
t3
4.5V
t4
t5
Figure 22. Switching Losses and Q_G
5V
R_D
VIN
HDRV
SW
C_GD
R_GATE
G
C_GS
Figure 23. Drive Equivalent Circuit
The upper graph in Figure 22 represents Drain-to-
Source Voltage (V_DS) and Drain Current (I_D) waveforms.
The lower graph details Gate-to-Source Voltage (V_GS)
vs. time with a constant current charging the gate. The x-
axis is representative of Gate Charge (Q_G). C_ISS = C_GD
+ C_GS and it controls t1, t2, and t4 timing. C_GD receives
the current from the gate driver during t3 (as V_DS is fall-
ing). Obtain the gate charge (Q_G) parameters shown on
the lower graph from the MOSFET datasheets.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1's switching losses
occur during the shaded time when the MOSFET has
voltage across it and current through it.
Losses are given by (EQ. 10), (EQ. 11), and (EQ. 12):
P_UPPER = P_SW + P_COND
(EQ. 10)
P_SW
=
⎛
⎝
V_{-----D---S--2---}×_-----I_--L-
×
2
×
t_{s⎠⎞}
F_SW
(EQ. 11)
P_COND
=
⎛
⎝
V_{---V--O---I-UN---T--⎠⎞}
× I_{O2 UT} × R_DS(ON)
(EQ. 12)
where P_UPPER is the upper MOSFET's total losses and
P_SW and P_COND are the switching and conduction losses
for a given MOSFET. R_DS(ON) is at the maximum junction
temperature (T_J) and t_S is the switching period (rise or
fall time) and equals t2+t3 (Figure 22.).
The driver's impedance and C_ISS determine t2 while t3's
period is controlled by the driver's impedance and Q_GD.
Since most of t_S occurs when V_GS = V_SP, assume a con-
stant current for the driver to simplify the calculation of t_S
using the following equation:
t_s = ^Q---_I--_DG---_r-⁽-_i-^S-_v--_e-^W--_r--⁾ ≈ _⎝⎛---_{R----------D----V----r---}^Q-_{iC--v------eC-}^G-----_r---⁽-–--+-^S-----_V--^W_-R-----_S----⁾_{G----P----a------t----e---⎠⎞}--
(EQ. 13)
Most MOSFET vendors specify Q_GD and Q_GS. Q_G(SW)
can be determined as:
Q_G(SW) = Q_GD + Q_GS – Q_TH where Q_TH is the gate
charge required to reach the MOSFET threshold (V_TH).
Note that for the high-side MOSFET, V_DS equals V_IN,
which can be as high as 20V in a typical portable appli-
cation. Include the power delivered to the MOSFET's
(P_GATE) in calculating the power dissipation required for
the FAN5069.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
14
www.fairchildsemi.com