FIN12AC_08 Datasheet, PDF (17/21 Pages) Fairchild Semiconductor – Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges

AC Loading and Waveforms (Continued)
CKSI-
CKSI+
DSI+
DSI-
t_{S_DS}
V_DIFF=0
t_{H_DS}
V_DIFF=0 V_ID/2
Figure 16. Differential Input
Setup and Hold Times
CKSO-
CKSO+
V_DIFF = 0
DSO+
DSO-
V_DIFF = 0
V_ID / 2
t_SPOS
Figure 17. Differential Output Signal Skew
CKREF
t_TPPLD0
t_TPPLD1
CKS0
Note: CKREF Signal can be stopped either High or LOW.
Figure 18. PLL Loss of Clock Disable Time
S1 or S2
CKS0
Figure 19. PLL Power-Down Time
t_PLZ(HZ)
S1 or S2
t_PZL(ZH)
DS+,CKS0+
DS–,CKS0-
HIGHZ
Note: CKREF must be active and PLL must be stable.
Figure 20. Serializer Enable and Disable Time
t_PLZ(HZ)
S1 or S2
t_PZL(ZH)
DP
Note: If S1(2) transitioning, then S2(1) must = 0 for test to be valid.
Figure 21. Deserializer Enable
and Disable Times
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
17
www.fairchildsemi.com