FIN12AC_08 Datasheet, PDF (13/21 Pages) Fairchild Semiconductor – Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges

AC Electrical Characteristics
Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified.
Typical values are given for V_DD = 2.775V and T_A = 25°C. Positive current values refer to the current flowing into
device and negative values refer to current flowing out of pins. Voltages are referenced to GROUND unless otherwise
specified (except ΔV_OD and V_OD).
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
Serializer Input Operating Conditions
t_TCP
CKREF Clock Period
(5MHz – 40MHz)
CKREF = STROBE
Figure 13
S2=1 S1=0
71.0
S2=1 S1=1 35.0
200
100
ns
S2=0 S1=1 25.0
50.0
ƒ_REF
CKREF Frequency Relative to
STROBE Frequency
CKREF does not =
S2=1 S1=0
1.1 x
f_STROBE
STROBE
S2=1 S1=0
40
14
MHz
S2=0 S1=1
28
t_CPWH
t_CPWL
t_CLKT
t_SPWH
CKREF Clock High Time
CKREF Clock Low Time
LVCMOS Input Transition Time
STROBE Pulse Width HIGH/LOW
Figure 13
Figure 13
0.2
0.5
T
0.2
0.5
T
90.0 ns
(T x 4)/14
(T x 12)/14 ns
S2=0 S1=1 280
540
f_MAX Maximum Serial Data Rate
CKREF x 14
S2=1 S1=0 70
196 ^Mb/s
S2=1 S1=1 140
392
t_STC DP_(n) Setup to STROBE
DIRI = 1
2.5
ns
t_HTC DP_(n) Hold to STROBE
Figure 3 (f = 5MHz)
2.0
ns
Serializer AC Electrical Characteristics
t_TCCD
Transmitter Clock Input to Clock
Output Delay
t_SPOS CKSO Position Relative to DS⁽³⁾
PLL AC Electrical Characteristics
DIRI = 1, a=(1/f)/14
CKREF = STROBE,
Figure 17
23a+1.5
-200
21a+6.5 ns
200
ps
t_TPLLS0
Serializer Phase-Lock Loop
Stabilization Time
Figure 15
200
µs
t_TPLLD0 PLL Disable Time Loss of Clock
t_TPLLD1 PLL Power-Down Time⁽⁴⁾
Figure 18
Figure 19
Deserializer AC Electrical Characteristics
30.0 µs
20.0 ns
t_RCOP
Deserializer Clock Output
(CKP OUT) Period
Figure 14
17.8
200
ns
t_RCOL CKP OUT Low Time
t_RCOH CKP OUT High Time⁽⁶⁾
Figure 14 (Rising Edge Strobe)
Serializer source STROBE =
CKREF
where a = (1/f)/14
7a–3
7a–3
7a+3 ns
7a+3 ns
t_PDV Data Valid to CKP LOW⁽⁶⁾
Figure 14 (Rising Edge Strobe)
where a = (1/f)/14
7a–3
7a+3 ns
t_ROLH Output Rise Time (20% to 80%)
t_ROHL Output Fall Time (80% to 20%)
C_L = 5pF
Figure 11
3.5
7.0
ns
3.5
7.0
ns
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
13
www.fairchildsemi.com