FIN12AC_08 Datasheet, PDF (14/21 Pages) Fairchild Semiconductor – Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges

Notes:
3 Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
4 The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies
dependent upon the operating mode of the device.
5 Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when
the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI
and jitter effects.
6 Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP
occurs approximately 8 bit times after a data transition or 6 bit times after the falling edge of CKSO. Variation of the
data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP path and
propagation delay differences on the various data pins. Note that if the CKREF is not equal to STROBE for the
serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13 bit times.
Control Logic Timing Controls
Symbol
Parameter
Test Conditions
t_{PHL_DIR},
t_{PLH_DIR}
t_PLZ, t_PHZ
Propagation Delay
DIRI-to-DIRO
Propagation Delay
DIRI-to-DP
DIRI LOW-to-HIGH or HIGH-to-LOW
DIRI LOW-to-HIGH
t_PZL, t_PZH
Propagation Delay
DIRI-to-DP
DIRI HIGH-to-LOW
t_PLZ, t_PHZ
Deserializer Disable Time
S0 or S1 to DP
DIRI = 0, S1(2) = 0 and S2(1) = LOW-to-HIGH
Figure 21
t_PZL, t_PZH
Deserializer Enable Time
S0 or S1 to DP⁽⁷⁾
DIRI = 0, S1(2) = 0 and S2(1) = LOW-to-HIGH
Figure 21
t_PLZ, t_PHZ
Serializer Disable Time
S0 or S1 to CKSO, DS
DIRI = 1, S1(2) = 0 and S2(1) = HIGH-to-LOW
Figure 20
t_PZL, t_PZH
Serializer Enable Time
S0 or S1 to CKSO, DS
DIRI = 1, S1(2) and S2(1) = LOW-to-HIGH
Figure 20
Min. Typ. Max. Units
17 ns
25 ns
25 ns
25 ns
2
µs
25 ns
65 ns
Note:
7 Serializer enable time includes the amount of time required for internal voltage and current references to stabilize.
This time is significantly less than the PLL lock time and does not limit overall system startup time.
Capacitance
Symbol
Parameter
Test Conditions
C_IN
C_IO
C_IO-DIFF
Capacitance of Input Only Signals, CKREF,
STROBE, S1, S2, DIRI
Capacitance of Parallel Port Pins DP[1:12]
Capacitance of Differential I/O Signals
DIRI = 1, S1 = 0, S2=0,
V_DD = 2.5V
DIRI = 1, S1 = 0, S2=0,
V_DD = 2.5V
DIRI = 1, S2=0, S1 = 0,
V_DD = 2.5V
Min. Typ. Max. Units
2
pF
2
pF
2
pF
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
14
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