FAN5182_08 Datasheet, PDF (17/19 Pages) Fairchild Semiconductor – Adjustable Output, 1-, 2-, or 3-Phase Synchronous Buck Controller

PCB Layout Guidelines
General Recommendations
To achieve the best performance, a PCB with at least four
layers is recommended. When designing the layout, keep
in mind that each square unit of 1-ounce copper has
resistance of ~0.53mΩ at room temperature.
Whenever high currents must be routed to a different
PCB layers, vias should be used properly to create
several parallel current paths so the resistance and
inductance introduced by these current paths are
minimized and via current rating is not exceeded.
If critical signal traces must be routed close to power
circuitry, a signal ground plane must be interposed
between those signal lines and the traces of the power
circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making
signal ground a bit noisier.
An analog ground island should be used around and
under the FAN5182 as a reference for the components
associated with the controller. The analog ground should
be connected to the power ground at a single point.
The components around the FAN5182 should be close
to the controller with short traces. The output capacitors
should be placed as close as possible to the load. If the
load is distributed, the capacitors should also be
distributed in proportion to the respective load.
Power Circuitry Recommendations
The PCB layout starts with high-frequency power
component placement. Try to minimize stray inductance
of the MOSFET half bridge, which is composed of the
input capacitors and top and bottom MOSFETs. A good
practice is to use short and wide traces or copper pours
to minimize the inductance in the MOSFET half bridge.
Failure to do so can lead to severe phase node ringing.
A snubber circuit is always recommended to partly kill
the phase node switching noise.
Whenever using a power dissipating component; for
example, a power MOSFET that is soldered to the PCB;
the proper use of vias, both directly on the mounting
pad and immediately surrounding the mounting pad is
recommended. Make a mirror image of the power pad
being used on the component side to heat sink the
MOSFETs on the opposite side of the PCB. Use large
copper pour for high-current traces to lower the
electrical impedance and help dissipate heat. Do not
make the switching node copper pour unnecessarily
large, since it could radiate noise.
An undisturbed solid power ground plane should be
used as one of the inner layers.
Signal Circuitry Recommendations
The output voltage is sensed from the FB and the
FBRTN pins. To avoid differential mode noise pickup in
these differential sensed traces, the loop area between
the FB and FBRTN traces should be minimized. In other
words, the FB and FBRTN traces should be routed
adjacent to each other with minimum spacing on top of
the analog / power ground plane back to the controller.
The signal traces connecting to the switch nodes should
be tied as close as possible to the inductor pins. The
CSREF sense trace should be connected to the second
nearest inductor pin to the controller.
Detailed step-by-step PCB layout instructions are
available from Fairchild upon request.
© 2005 Fairchild Semiconductor Corporation
FAN5182 • Rev. 1.1.3
17
www.fairchildsemi.com