FAN5182_08 Datasheet, PDF (12/19 Pages) Fairchild Semiconductor – Adjustable Output, 1-, 2-, or 3-Phase Synchronous Buck Controller

Application Information
Design parameters for a typical high-current DC/DC
buck converter, as shown in Figure 7, follow. This is a
multiphase, current-mode control implementation. The
equations shown are interdependent and must be
followed in the sequence shown. For other
implementations, adjust the design requirements.
NOTE: A complete MathCAD^® control design program
is available from Fairchild upon request.
Design Requirements:
ƒ Input voltage (VIN) = 12V
ƒ Output voltage (VOUT) = 1.8V
ƒ Duty cycle (D) = 0.15
ƒ Output current IO = 55A
ƒ Maximum output current (ILIM) = 110A
ƒ Number of phases (n) = 3
ƒ Switching frequency per phase (fSW) = 250kHz
Setting the Clock Frequency
The FAN5182 uses fixed-frequency control architecture.
The frequency is set by an external timing resistor (RT).
The clock frequency and the number of phases
determine the switching frequency per phase, which
relates directly to switching losses and the sizes of the
inductors and the input and output capacitors. With n =
3 for three phases, a clock frequency of 750kHz sets
the switching frequency, fSW, of each phase to 250kHz,
which represents a practical trade-off between the
switching losses and the sizes of the output filter
components.
Equation 1 shows that to achieve a 750kHz oscillator
frequency, the correct value for RT is 255kΩ.
Alternatively, the value for RT can be calculated using:
RT =
1
− 27KΩ
n × fSW × 4.7pF
RT =
1
− 27KΩ = 256KΩ
(1)
3 × 250kHz × 4.7pF
where 4.7pF and 27kΩ are internal IC component
values. For good initial accuracy and frequency stability,
a 1% resistor is recommended. The closest standard
1% value for this design is 255kΩ.
NOTE: For a single-phase application, set the oscillator
frequency to two times the required per-phase switching
frequency. This can be done buy substituting “2 x fSW”
for “fSW” in Equation 1.
Soft-Start and Current-Limit Latch-off
Delay Time
Because the soft-start and current-limit latch-off delay
functions share the DELAY pin, these two parameters
must be considered together. The first step is to set
CDLY for the soft-start ramp. This ramp is generated with
a 20µA internal current source. The value of RDLY has a
second-order impact on the soft-start time because it
sinks part of the current source to ground. As long as
RDLY is greater than 200kΩ, this effect is minor.
The value for CDLY can be approximated using:
CDLY
=
⎜⎜⎝⎛ ^20μA
−
V_REF
2 × RDLY
⎟⎟⎠⎞ ^×
tSS
V_REF
(2)
where tSS is the desired soft-start time. Assuming an
RDLY of 390kΩ and a desired soft-start time of 3ms, CDLY
is 71nF. The closest standard value for CDLY is 68nF.
Once CDLY is chosen, RDLY can be calculated for the
current-limit latch-off time, using:
RDLY = ^{1.96 × tDELAY}
(3)
CDLY
If the result for RDLY is less than 200kΩ, a smaller soft-
start time should be considered, by recalculating the
equation for CDLY, or a longer latch-off time should be
used. RDLY should never be less than 200kΩ. In this
example, a delay time of 9ms results in RDLY = 259kΩ.
The closest standard 1% value is 261kΩ.
Inductor Selection
The inductance determines the ripple current in the
inductor. Small inductance leads to high ripple current,
which increases the output ripple voltage and
conduction losses in the MOSFETs and vice versa. In
any multiphase converter, it's recommended to design
the peak-to-peak inductor ripple current to be less than
50% of the maximum inductor DC current.
Equation 4 shows the relationship among the inductance,
oscillator frequency, and peak-to-peak ripple current:
IR = ^{VOUT × (1 − D)}
f_SW × L
(4)
Equation 5 can be used to determine the minimum
inductance based on a given output ripple voltage:
L ≥ ^{VOUT × Rx × (1− (n × D))}
(5)
fSW × VRIPPLE
where RX is the ESR of output bulk capacitors.
Solving Equation 5 for a 20mV peak-to-peak output
ripple voltage and 3mΩ RX yields:
L ≥ ^{1.8V × 0.7mΩ × (1− (3 × 0.15))} = 277nH
250kHz × 10mV
(6)
If the resulting ripple voltage is too low, the inductance
can be reduced until the desired ripple voltage is
achieved. In this example, a 600nH inductor is a good
starting point that produces a calculated ripple current
of 6.6A. The inductor should not saturate at the peak
current of 21.6A and should be able to handle the total
power dissipation created by the copper and core loss.
Another important factor in the inductor design is the
Direct Conversion Receiver (DCR), which is used for
measuring the phase current. A large DCR can cause
excessive power losses, whereas too small DCR can
increases measurement error. For this design, a DCR
of 1.4mΩ was chosen.
© 2005 Fairchild Semiconductor Corporation
FAN5182 • Rev. 1.1.3
12
www.fairchildsemi.com