FAN5182_08 Datasheet, PDF (14/19 Pages) Fairchild Semiconductor – Adjustable Output, 1-, 2-, or 3-Phase Synchronous Buck Controller

Knowing the maximum output current and the maximum
allowed power dissipation, determine the required
RDS(ON) for the MOSFET. For example, with D-PAK
MOSFETs operating up to ambient temperature of
50°C, a safe limit for PSF is around 1W to 1.5W at
120°C junction temperature. Therefore, in this example,
RDS(SF) (per MOSFET) < 7.5mΩ. This RDS(SF) is typically
measured at junction temperature of about 120°C. In
this example, select a lower-side MOSFET with 4.8mΩ
at 120°C.
WARNING: The RDS of the bottom FET is also used to
measure the current flowing in the phase. This is used
for current balance and for the current-feedback loop.
Using a FET with too low an RDS can result in poor
current balance and too large a ramp resistor
calculation in Equation 18.
Typically, for main MOSFETs, a low gate charge (CISS)
device is preferred, but low gate charge MOSFETs
usually have higher on resistance. Select a device that
meets total power dissipation around 1.5W for a single
D-PAK MOSFET.
In this example, a FDD6296 is selected as the main
MOSFET (three total; nMF = 3), with a CISS = 1440pF,
and RDS(MF) = 9mΩ (at TJ = 120°C). A FDD8896 is
selected as the synchronous MOSFET (three total; nSF
= 3), with CISS = 2525pF and RDS(SF) = 5.4mΩ (at TJ =
120°C). The synchronous MOSFET CISS is less than
6000pF. Solving for the power dissipation per MOSFET
at IO = 55A and IR = 6.6A yields 1.56W for each
synchronous MOSFET and 1.29W for each main
MOSFET. These numbers comply with the power
dissipation limit of around 1.5W per MOSFET.
Another important consideration for choosing the
synchronous MOSFET is the input and feedback
capacitance. The ratio of feedback to input capacitance
must be small (less than 10% is recommended) to
prevent accidentally turning on the synchronous
MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off
should not exceed the non-overlap dead time of the
MOSFET driver (40ns typical for the FAN5109). The
output impedance of the driver is approximately 2Ω and
the typical MOSFET input gate resistances are about
1Ω to 2Ω; therefore, the total gate capacitance should
be less than 6000pF. In the event there are two
MOSFETs in parallel, the input capacitance for each
synchronous MOSFET should be limited to 3000pF.
The high-side (main) MOSFET power dissipation
consists of two elements: conduction and switching
losses. The switching loss is related to the main
MOSFET’s turn-on and turn-off time and the current and
voltage being switched. Based on the main MOSFET’s
switching speed (rise and fall time that the gate driver
can offer) and MOSFET input capacitance, the following
expression provides the approximate switching loss for
each main MOSFET:
P_S(MF)
=
2 × f_SW
×
V_CC × I_O
n_MF
× R_G
×
n_MF
n
× C_ISS
(15)
where:
One more item that needs to be considered is the
power dissipation in the driver for each phase. The
gate-drive loss is described in terms of the QG for the
MOSFETs and is given by the following equation:
P_DRV
=
⎡
⎢
⎣
f_SW
2×n
×
(n_MF
× Q_GMF
+ n_SF
×
Q_GSF
)
+
I_CC
⎤
⎥
×
V_CC
⎦
(17)
where:
QGMF is the total gate charge for each main MOSFET,
QGSF is the total gate charge for each synchronous
MOSFET.
ICC × VCC in Equation 17 represents the driver's standby
power dissipation. For the FAN5109, the maximum
dissipation should be less than 400mW. In this
example, with ICC = 5mA, QGMF = 25nC, and QGSF =
50nC; there is 285mW in each driver, which is below
the 400mW dissipation limit. See the Thermal
Information table in the FAN5109 datasheet for details.
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the
internal PWM ramp. The value of this resistor is chosen
to provide the best combination of phase-current
balance, stability, and transient response.
The following expression is used to determine the
optimum value:
nMF is the total number of main MOSFETs;
RG is the total gate resistance (2Ω for the FAN5109 and
about 1Ω for typical logic level N-channel MOSFETs,
total RG = 3Ω);
CISS is the input capacitance of the main MOSFET.
Note that adding more main MOSFETs (nMF) does not
help lower the switching loss for each main MOSFET; it
can only reduce conduction loss. The most efficient way
to reduce switching loss is to use low-gate charge /
capacitance devices.
The conduction loss of the main MOSFET is given by:
P_C(MF)
=
D×
⎢⎢⎣⎡⎜⎜⎝⎛
I_O
n_MF
⎟⎟⎠⎞²
+
1
12
×
⎜⎜⎝⎛
n × I_R
n_MF
⎟⎟⎠⎞
2
⎤
⎥
⎥
⎦
× R_DS(MF)
(16)
R_R
=
3× A_D
A_R ×L
× R_DS(ON)(SF)
× C_R
(18)
R_R
=
0.2 × 320nH
3 × 5 × 2.4mΩ × 5pF
=
356kΩ
(19)
where:
ƒ AR is the internal ramp amplifier gain,
ƒ AD is the current balancing amplifier gain,
ƒ RDS(ON)(SF) is the equivalent low-side MOSFET on
resistance,
ƒ CR is the internal ramp capacitor value.
The closest standard 1% resistor value is 332kΩ.
where RDS(MF) is the on resistance of the main MOSFET.
© 2005 Fairchild Semiconductor Corporation
FAN5182 • Rev. 1.1.3
14
www.fairchildsemi.com