FAN5182_08 Datasheet, PDF (15/19 Pages) Fairchild Semiconductor – Adjustable Output, 1-, 2-, or 3-Phase Synchronous Buck Controller

WARNING: The ramp resistor should be less than 1MΩ
to ensure that board contaminates don’t affect the
ramp. If the calculated value is greater than 1MΩ, verify
that the RDS of the bottom FET is not too low.
Internal ramp voltage magnitude can be calculated by:
V_R
=
A_R × (1− D) × V_OUT
R_R × C_R × f_SW
(20)
V_R
=
0.2 × (1− 0.15) ×1.8V
357KΩ × 5pF × 250kHz
=
686mV
(21)
The size of the internal ramp can be made larger or
smaller. If it is made larger, stability and transient
response improve, but thermal balance degrades. If the
ramp is made smaller, thermal balance improves, but
transient response and stability degrade. The factor of
three in the denominator of Equation 18 sets a ramp
size with optimal balance for good stability, transient
response, and thermal balance.
Ramp Resistor Selection for Voltage-Mode
Control
When configured for single-phase voltage-mode control
(SW pin grounded), the ramp resistor is selected to
produce a fixed-ramp voltage. For example, to create a
ramp voltage of 1V, the following equation is used:
( ) _RR
=
0.2 × V_IN − V_REF × V_OUT
V_IN × f_SW × C_R × d_Vr
− 2000
(22)
where:
ƒ RR is the ramp resistor connected between VIN and
FAN5182 RAMPADJ pin 9
ƒ 0.2 is the internal current transfer ratio between
RRAMPADJ and the PWM ramp current source(s)
ƒ VIN is the input voltage (12V)
ƒ VREF is the internally generated reference (0.8V)
ƒ VOUT is the output voltage
ƒ CR is the internal PWM ramp capacitor, 5pF
ƒ fsw is the switching frequency defined as (Master
Osc / 2) for single- and dual-phase operation and
(Master Osc / 3) for three-phase operation
ƒ dVr is the target peak ramp voltage; 1V is a typical
target voltage.
Current Limit Set Point
The current-limit threshold is set with a 3V source VLIM
across RLIM with a gain of 10.4mV/µA (ALIM).
RLIM can be found using:
R _LIM
=
A _LIM × V_LIM
V _DRPMAX
(23)
WARNING: Be sure to take into account the peak
current ripple current and the increase in inductor DCR
at high temperatures if the inductor is not temperature
compensated.
If RLIM is greater than 500kΩ, the actual current-limit
threshold may be lower than the intended value. Some
adjustment for RLIM may be needed. Here, ILIM is the
average current limit for the output of the supply. In this
example, using the VDRPMAX value of 110mV from
Equations 7 and 8 and choosing a peak current limit of
110A for ILIM results in RLIM = 284kΩ, for which 287kΩ is
chosen as the nearest 1% value.
The per-phase current limit is determined by:
I_PHLIM
≅
V_COMP(MAX) − V_R − V_BIAS
A _D × R_DS(MAX)
+ ^IR
2
(24)
Closed-Loop Compensation Design
NOTE: This section does not apply in a voltage-mode
control configuration.
Optimum compensation assures the best possible load
regulation and transient response of the regulator. The
target of the compensation design is to achieve
reasonably high control bandwidth with sufficient phase
and gain margin.
The power stage of the synchronous buck converter
consists of two poles and one zero. A two-pole, one-
zero compensator of the voltage error amplifier is
adequate for proper compensation if the output bulk
capacitors are electrolytic types (low ESR zero).
Equations 25-27 are able to yield an approximate
starting point for the design. To further optimize the
design, some bench adjustments may be necessary.
⎜⎛
⎟⎞
( ) ^CA
=
C_X ×R_X
R_B2
⎜
×⎜
⎜
⎜⎝
⎜⎜⎝⎛
V_R
V_OUT
n×R_X
× R_{L ⎟⎟⎠⎞} + A_D ×_RDS
⎟
⎟
⎟
⎟⎠
(25)
R_A
=
R_B2
C_X ×R_X
× ^VR
V_OUT
×
⎜⎜⎝⎛
n
L
×R
X
− ^{A D × RDS}
2 × f_SW × R _X
− C_X × R_{X ⎟⎟⎠⎞}
(26)
C_FB
=
1
2 × n × f_SW
×R_A
(27)
If CX is 6000µF (five 1200µF capacitors in parallel) with
an equivalent ESR of 3mΩ, the equations above give
the following compensation values:
CA = 1.33nF, RA= 6.05kΩ, CFB = 110pF
(28)
Selecting the nearest standard value for each of these
components yields:
CA = 1.2nF, RA = 6.04kΩ, and CFB = 100pF
(29)
As mentioned above, this compensation design scheme
is typically good for applications using electrolytic type
capacitors, where the capacitor ESR zero can roughly
cancel one of the power stage poles. However, for all
ceramic capacitor types of applications, since the
capacitor ESR zero can be very high, a three-pole, two-
zero compensator should be used.
© 2005 Fairchild Semiconductor Corporation
FAN5182 • Rev. 1.1.3
15
www.fairchildsemi.com