FAN3100_09 Datasheet, PDF (15/21 Pages) Fairchild Semiconductor – Single 2A High-Speed, Low-Side Gate Driver

Layout and Connection Guidelines
The FAN3100 incorporates fast reacting input circuits,
short propagation delays, and powerful output stages
capable of delivering current peaks over 2A to facilitate
voltage transition times from under 10ns to over 100ns.
The following layout and connection guidelines are
strongly recommended:
ƒ Keep high-current output and power ground paths
separate from logic input signals and signal ground
paths. This is especially critical when dealing with
TTL-level logic thresholds.
ƒ Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and other
surrounding circuitry.
ƒ The FAN3100 is available in two packages with
slightly different pinouts, offering similar
performance. In the 6-pin MLP package, Pin 2 is
internally connected to the input analog ground and
should be connected to power ground, Pin 5,
through a short direct path underneath the IC. In
the 5-pin SOT23, the internal analog and power
ground connections are made through separate,
individual bond wires to Pin 2, which should be
used as the common ground point for power and
control signals.
ƒ Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
triggering. These effects can be especially obvious
if the circuit is tested in breadboard or non-optimal
circuit layouts with long input, enable, or output
leads. For best results, make connections to all
pins as short and direct as possible.
ƒ The turn-on and turn-off current paths should be
minimized as discussed in the following sections.
Figure 43 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn
the MOSFET on. The current is supplied from the local
bypass capacitor, CBYP, and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance
in the path should be minimized. The localized CBYP
acts to contain the high peak current pulses within this
driver-MOSFET circuit, preventing them from disturbing
the sensitive analog circuitry in the PWM controller.
Figure 44 shows the current path when the gate driver
turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
Figure 44. Current Path for MOSFET Turn-Off
Truth Table of Logic Operation
The FAN3100 truth table indicates the operational
states using the dual-input configuration. In a non-
inverting driver configuration, the IN- pin should be a
logic low signal. If the IN- pin is connected to logic high,
a disable function is realized, and the driver output
remains low regardless of the state of the IN+ pin.
IN+
IN-
OUT
0
0
0
0
1
0
1
0
1
1
1
0
In the non-inverting driver configuration in Figure 45,
the IN- pin is tied to ground and the input signal (PWM)
is applied to IN+ pin. The IN- pin can be connected to
logic high to disable the driver and the output remains
low, regardless of the state of the IN+ pin.
Figure 45. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver application shown in Figure 46, the
IN+ pin is tied high. Pulling the IN+ pin to GND forces the
output low, regardless of the state of the IN- pin.
Figure 43. Current Path for MOSFET Turn-On
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.2
15
Figure 46. Dual-Input Driver Enabled,
Inverting Configuration
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