FXLA2203 Datasheet, PDF (12/16 Pages) Fairchild Semiconductor – Dual-Mode, Dual-SIM-Card Level Translator

Power-Up / Power-Down Sequence
Table 4. Power Supply Pins
Pin
Name
Function
1
VCC
EN and CH_Swap Supply
2
VCC_H_1
Host 1 Supply
3
VCC_H_2
Host 2 Supply
4
VCC1
Power Switch 1 Input
5
VCC2
Power Switch 2 Input
The V_CC host power sequencing is non preferential;
however, V_CC must be higher or equal to V_CC1 and V_CC2.
The Enable pin must be LOW while V_CC1 and V_CC2 ramp
up to valid supply voltages or ramp down to 0V.
A pull-up resistor tying enable to ground should be used
to ensure that bus contention, excessive currents, or
oscillations do not occur during power up or power
down. The size of the pull-up resistor is based upon the
current sinking capability of the device driving the
Enable pin.
Recommended power-up sequence (see Figure 16):
1. Apply power to VCC.
2. Assert EN LOW (FXLA2203 disabled).
3. Apply power to VCC1, VCC2, VCC_H_1, and
VCC_H_2.
4. Assert EN HIGH (FXLA2203 enabled).
5. Begin activation timing (see Figure 14).
Recommended power-down sequence (see Figure 17):
1. Complete deactivation timing (see Figure 15).
2. Assert EN LOW (FXLA2203 disabled).
3. Ramp down power to VCC1, VCC2, VCC_H_1,
and VCC_H_2.
4. Once VCC1 and VCC2 are OFF, ramp down VCC.
VCC_Cardn
RST_n
CLK_n
I/O_n
EN
CH_Swap
VCC1, VCC2
VCC_H_n
Power-Up
Sequencing
Begin Activation
Timing per ISO7816
3 2006
A
BC
Z Z ZZ
Z Z ZZ
Z Z ZZ
Z Z ZZ
VCC
RST_H_n
CLK_H_n
I/O_H_n
Figure 16. Power-Up Sequencing
Notes:
23. A=VCC becomes a valid voltage, EN=LOW.
24. B=VCC1, VCC2, and VCC_H_n become valid
voltages, EN=LOW.
25. C=FXLA2203 enabled (EN goes HIGH), ready for
activation (ISO7816-3).
Figure 17. Power-Down Sequencing
Notes:
26. A=Disable FXLA2203, bring EN LOW.
27. B=Ramp down VCC1, VCC2, and VCC_H_n.
28. C=Ramp down VCC once VCC1 and VCC2 are off.
© 2010 Fairchild Semiconductor Corporation
FLXA2203 • Rev. 1.0.5
12
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