XRT73L02M Datasheet, PDF (9/46 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02M
REV. 1.0.0
RECEIVE INTERFACE
PIN #
91
36
SIGNAL NAME
RxCLK_0
RXCLK_1
92
RPOS_0
35
RPOS_1
93 RNEG_0/LCV_0
34 RNEG_1/LCV_1
8
RRING_0
18
RRING_1
9
RTIP_0
17
RTIP_1
29
RxClkINV/
CS
TYPE
O
O
O
I
I
I
DESCRIPTION
Receive Clock Output - Channel 0:
Receive Clock Output - Channel 1:
By default, RPOS and RNEG data sampled on the rising edge RxCLK..
Set the RxCLKINV bit or tie RClkINV pin “High” to sample RPOS/RNEG data
on the falling edge of RxCLK
Receive Positive Data Output - Channel 0:
Receive Positive Data Output - Channel 1:
NOTE: If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero
suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V",
"B00V") is removed and replaced with ‘0’.
Receive Negative Data Output/Line Code Violation Indicator - Channel 0:
Receive Negative Data Output/Line Code Violation Indicator - Channel 1:
In Dual Rail mode, a negative pulse is output through RNEG.
Line Code Violation Indicator - Channel n:
If configured in Single Rail mode then Line Code Violation will be output.
Receive Ring Input - Channel 0:
Receive Ring Input - Channel 1:
These pins along with RTIP receive the bipolar line signal from the remote DS3/
E3/STS-1 Terminal.
Receive TIP Input - Channel 0:
Receive TIP Input - Channel 1:
These pins along with RRING receive the bipolar line signal from the Remote
DS3/E3/STS-1 Terminal.
Hardware Mode: RxClk INVERT
Host Mode: Chip Select:
Function of this pin depends on whether the XRT73L02M is configured to oper-
ate in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures the Receiver Sec-
tion of all channels to invert the RxClk_n output signals and outputs the recov-
ered data via RPOS_n and RNEG_n on the falling edge of RxClk_n.
NOTE: If the XRT73L02M is configured in HOST mode, this pin functions as CS
input pin (please refer to the pin description for Microprocessor Interface).
7