XRT73L02M Datasheet, PDF (39/46 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

xr
REV. 1.0.0
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02M
TABLE 17: REGISTER MAP DESCRIPTION - CHANNEL 0
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0 DMOIE_n Writing a “1” to this bit enables an interrupt when the
0
no transmission detected on channel output.
D1 RLOSIE_n Writing a “1” to this bit enables an interrupt when
0
Receive Los of Signal is detected.
D2 RLOLIE_n Writing a “1” to this bit enables an interrupt when
0
0x01 (ch 0) R/W Interrupt
Receive Loss of Lock condition is detected
0x09 (ch 1)
Enable
D3
Reserved
0
(source
level)
D7-D4
Reserved
D0 DMOIS_n This bit is set every time a DMO status change has
0
occurred since the last cleared interrupt.This bit is
cleared when the register bit is read.
D1 RLOSIS_n This bit is set every time a RLOS status change has
0
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
0x02 (ch 0) Reset Interrupt
D2 RLOLIS_n This bit is set every time a RLOL status change has
0
0x0A (ch 1) on Status
Read (source
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
level)
D3
Reserved
0
D7-D4
Reserved
D0 DMO_n This bit is set every time the MTIP_0/MRing_0 input
0
pins have not detected any bipolar pulses for 128
consecutive bit periods.
D1 RLOS_n This bit is set every time the receiver declares an
0
LOS condition.
D2 RLOL_n This bit is set every time when the receiver declares
0
a Loss of Lock condition.
D3
Reserved
0
0x03 (ch 0) Read Alarm Sta- ^{D4 ALOS_n This bit is set every time the receiver declares Ana-}
0
0x0B (ch 1) Only tus
log LOS condition.
D5 DLOS_n This bit is set every time the receiver declares Digital
0
LOS condition.
D6 PRBSLS_n This bit is set every time the PRBS detector is not in
0
sync.
D7
Reserved
37