XRT73L02M Datasheet, PDF (13/46 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

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TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02M
REV. 1.0.0
MODE SELECT
PIN #
SIGNAL NAME
2
E3_0
24
E3_1
3
STS1/DS3 _0
23
STS1/DS3 _1
26
HOST/HW
100
SR/DR
TYPE
I
I
I
I
DESCRIPTION
E3 Mode Select Input
A "High" on this pin configures in E3 mode.
A "Low" on this pin configures in either STS-1 or DS3 mode depending on the
settings on pins 3 and 23..
NOTES:
1. This pin is internally pulled down
2. This pin is ignored if configured to operate in HOST mode.
STS-1/DS3 Select Input
A “High” on these pins configures in STS-1 mode.
A “Low” on these pins configures in DS3 mode.
These pins are ignored if the E3_n pins are set to “High”.
NOTES:
1. This pin is internally pulled down
2. This pin is ignored if configured to operate in HOST mode.
Host/Hardware Mode:
Tie this pin “High” to configure in Host mode and “Low” for Hardware mode.
Single-Rail/Dual-Rail Select:
Setting this “High” configures both the Transmitter and Receiver to operate in
Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In
Single-rail mode, TNEG_n pin should be grounded.
Setting this “Low” configures both the Transmitter and Receiver to operate in
Dual-rail mode and disables the B3ZS/HDB3 Encoder and Decoder.
NOTE: This pin is internally pulled down.
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)
PIN #
29
SIGNAL NAME
CS
RxCLKINV
30
SCLK
TxCLKINV
TYPE
I
I
DESCRIPTION
Microprocessor Serial Interface - Chip Select
Tie this “Low” to enable the communication with the Microprocessor Serial Inter-
face.
NOTE: If configured in Hardware Mode, this pin functions as RxClkINV.
Serial Interface Clock Input
The data on the SDI pin is sampled on the rising edge of this signal. Additionally,
during Read operations the Microprocessor Serial Interface updates the SDO
output on the falling edge of this signal.
NOTE: If configured in Hardware Mode, this pin functions as TxClkINV.
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