XRT73L02M Datasheet, PDF (32/46 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73L02M
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
As defined in ITU-T G.775, an LOS condition is also declared between 10 and 255 UI (or E3 bit periods) after
the actual time the LOS condition has occurred. The LOS condition is cleared within 10 to 255 UI after restora-
tion of the incoming line signal. Figure 20 shows the LOS declaring and clearing conditions.
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.
RTIP/
RRing
Actual Occurrence
of LOS Condition
Line Signal
is Restored
10 UI
255 UI
Time Range for
LOS Declaration
10 UI
255 UI
RLOS Output Pin
0 UI
G.775
Compliance
0 UI
Time Range for
LOS Clearance
G.775
Compliance
5.0.4.3 Muting the Recovered Data with LOS condition:
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the E3/
DS3/STS1CLK pin and output this clock on the RxClk_n output. In Single Frequency Mode (SFM), the clock re-
covery locks into the rate clock generated and output this clock on the RxClk_n pins. The data on the RPOS_n
and RNEG_n pins can be forced to zero by pulling the LOSMUT pin “High” (in Hardware Mode) or by setting
the LOSMUT_n bits in the individual channel control register to “1” (in Host Mode).
NOTE: When the LOS condition is cleared, the recovered data is output on RPOS_n and RNEG_n pins.
6.0 JITTER:
There are three fundamental parameters that describe circuit performance relative to jitter:
•
Jitter Tolerance (Receiver)
•
Jitter Transfer (Receiver/Transmitter)
•
Jitter Generation
6.0.1 JITTER TOLERANCE - RECEIVER:
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the jit-
ter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error rate
(BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal modulation of
the serial data bit sequence.
30