XRT73L02M Datasheet, PDF (40/46 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73L02M
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TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
TABLE 17: REGISTER MAP DESCRIPTION - CHANNEL 0
REV. 1.0.0
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
D0
D1
SYMBOL
DESCRIPTION
DEFAULT
VALUE
TxLEV_n ^{Set this bit for cable length greater than 225}
0
feet.
NOTE: See section 4.03 for detailed description.
TxClkINV_ Set this bit to sample the data on TPOS/TNEG pins
0
n
on the rising edge of TxClk.
D2 TAOS_n Set this bit to send a continuous stream of marks
0
0x04 (ch 0) R/W Transmit
(All Ones) out at the TTIP and TRING pins.
0x0C (ch 1)
Control
D3
Reserved
D4 INSPRBS_ Setting this bit causes the PRBS generator to insert
0
n
a single-bit error onto the transmit PRBS data
stream.
NOTE: PRBS Generator/Detector must be enabled
for this bit to have any effect.
D5 TxMON_n Setting this bit causes the driver monitor its own
0
transmit driver. When the transmit failure is
detected, DMO output pin goes “High” and DMOIS
bit is set.
When this bit is “0”, MTIP and MRing are connected
to other transmit channel for monitoring.
D7-D6
Reserved
D0 REQEN_n Set this bit to enable the Receive Equalizer.
0
NOTE: See section 5.01 for detailed description.
D1 RxMON_n Set this bit to configure the Receiver in monitoring
0
mode. In this mode, the Receiver can monitor a sig-
nal at the RTIP/RRING pins that has be attenuated
up to 20dB flat loss.
0x05 (Ch 0) R/W Receive
D2 LOSMUT_ Setting this bit causes the RPOS/RNEG outputs to
0
0x0D (Ch 1)
Control
n
“0” while the LOS condition is declared.
NOTE: If the bit has ben set, it will remain set even
after LOS condition is cleared.
D3 RxClkINV_ Set this bit to configure the Receiver to output
0
n
RPOS/RNEG data on the falling edge of RxClk_0.
D4 ALOSDIS_ Set this bit to disable the ALOS detector.
0
n
D5 DLOSDIS_ Set this bit to disable the DLOS detector.
0
n
D7-D6
Reserved
38