XRT73L02M Datasheet, PDF (35/46 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

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XRT73L02M
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
There are two distinct characteristics of jitter transfer: i) jitter gain (jitter peaking) defined as the highest ratio
above 0dB; and ii) jitter transfer bandwidth.The overall jitter transfer bandwidth is controlled by a low bandwidth
loop, typically using a voltage-controller crystal oscillator (VCXO).
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter.
6.0.3 JITTER GENERATION:
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and da-
ta recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is es-
sentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set ac-
cording to the data rate. In general, the jitter is measured over a band of frequencies.
7.0 SERIAL HOST INTERFACE:
A serial microprocessor interface is included in the XRT73L02M. The interface is generic and is designed to
support the common microprocessors/microcontrollers. The XRT73L02M is configured in Host mode when the
HOST/HW pin is tied “High”. The serial interface includes a serial clock (SClk), serial data input (SDI), serial
data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown in Figure
11.
The active low interrupt output signal (INT pin) indicates alarm conditions like LOS and DMO to the processor.
When configured in Host mode, the following input pins,TxLEV_n, TAOS_n, RLB_n, LLB_n, E3_n, STS-1/
DS3_n, REQEN_n are disabled and must be connected to ground.
The Table 14 below illustrates the functions of the shared pins in either Host mode or in Hardware mode.
PIN NUMBER
29
30
31
27
28
TABLE 12: FUNCTIONS OF SHARED PINS
IN HOST MODE
CS
SClk
SDI
SDO
INT
IN HARDWARE MODE
RxClkINV
TxClkINV
RxON
RxMON
LOSMUT
NOTE: While configured in Host mode, the TxON input pin will be active if the TxON_n bits in the control register are set to
“1”, and can be used to turn on and off the transmit output drivers. This permits a system designed for redundancy to
quickly switch out a defective line card and switch-in the backup line card.
ADDRESS
(HEX)
PARAMETER
NAME
0x00 APS/Redundancy
(read/write)
TABLE 13: REGISTER MAP AND BIT NAMES
DATA BITS
7
6
5
4
3
2
Reserved
RxON-1 RxON_0
Reserved
1
0
TxON-1 TxON_0
33