XR16M890IL32-0C Datasheet, PDF (9/63 Pages) Exar Corporation – UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.0 FUNCTIONAL DESCRIPTIONS
1.1 CPU Interface
There are 3 CPU interfaces that can be selected on the XR16M890. They are the Intel, Motorola and VLIO
bus interfaces. Note: no clock (crystal or external clock) is required for data bus transactions. Each bus cycle
is asynchronous.
1.1.1 Intel bus interface (16 mode)
The Intel bus interface consists of 8 data bits, 3 address lines and 3 control signals (CS#, IOR# and IOW#) for
data bus read/write transactions. In this mode, the interrupt output (INT) is active high. A typical data bus
interconnection is shown in Figure 4.
FIGURE 4. XR16M890 TYPICAL INTEL DATA BUS INTERCONNECTION
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
U AR T_IO R #
U AR T_IO W #
UART_CS#
U AR T_IN T
SLEEP /PW R D N
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR #
IO W #
CS#
IN T
SLEEP/PW R DN
RESET
VCC_BUS
16/68#
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
R I#
V L IO _ E N
GND
VCC_BUS
S erial Transceivers of
R S -2 3 2
R S -4 8 5
R S -4 2 2
O r Infrared
1.1.2 Motorola bus interface (68 mode)
The Motorola bus interface is similar to the Intel bus interface. This interface consists of 8 data bits, 3 address
lines, but only 2 control signals (CS# and R/W#) for data bus read/write transactions. In this mode, the
interrupt output (IRQ#) is an open-drain and active low. A typical data bus interconnection is shown in
Figure 5.
FIGURE 5. XR16M890 TYPICAL MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
R /W #
UART_CS#
U A R T_IR Q #
SLE EP /PW R D N
UART_RESET#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
VCC
IO R #
IO W #
vcc
CS#
VCC_BUS
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
R I#
VCC_BUS
S erial T ra nsceive rs of
R S -2 3 2
R S -4 8 5
R S -4 2 2
O r Infrared
IR Q #
SLEEP /PW R D N
RESET#
1 6 /6 8 #
VLIO _EN
GND
9