XR16M890IL32-0C Datasheet, PDF (6/63 Pages) Exar Corporation – UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
Pin Description
REV. 1.0.0
NAME
INT
(IRQ#)
RESET
(RESET#)
QFN-32 QFN-40 TQFP-48
TYPE
PIN#
PIN#
PIN#
DESCRIPTION
10
12
15
O _{When 16/68# pin is at logic 1 for Intel bus interface, this output}
(OD) become the active high device interrupt output. The output state is
defined by the user through the software setting of MCR[3]. INT is
set to the active mode when MCR[3] is set to a logic 1. INT is set to
the three state mode when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes the active low device interrupt output (open drain). An
external pull-up resistor is required for proper operation.
9
10
13
I _{When 16/68# pin is at logic 1 for Intel bus interface, this input}
becomes RESET (active high). When 16/68# pin is at logic 0 for
Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal reg-
isters and all outputs of the UART. The UART transmitter output will
be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period (see UART Reset Conditions).
DATA BUS INTERFACE - VLIO
VLIO_EN
28
37
45
I _{VLIO Bus Enable. When VLIO_EN pin is at logic 0, the bus interface}
is selected by the 16/68# pin. When VLIO_EN pin is at logic 1, the
VLIO bus interface is enabled and the 16/68# pin has no effect.
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
IOR#
8
9
9
I/O _{Multiplexed Address/Data lines [7:0]. The register address is}
7
8
8
latched on the rising edge of the LLA#. After the LLA# signal goes
6
7
7
5
6
6
high, the UART enters the data phase where the data is placed on
these lines.
4
5
5
3
4
4
2
3
3
1
2
2
13
16
10
I _{Read strobe (active low). The falling edge instigates an internal}
read cycle and retrieves the data byte from an internal register
pointed by the latched address. The UART places the data byte on
the data bus to allow the host processor to read it on the rising
edge.
IOW#
14
17
11
I _{Write strobe (active low). The falling edge instigates the internal}
write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the latched address.
CS#
15
18
12
I _{Chip select (active low). The falling edge starts the access to the}
UART. A read or write is determined by the IOR# and IOW# sig-
nals.
LLA#
31
40
48
I _{Latch Lower Address (active low). The register address is latched}
on the rising edge of the LLA# signal. After the LLA# goes high, the
device enters the data phase where the data is placed on the
AD[7:0] lines.
In the Intel/Motorola mode, this pin becomes A0.
6