XR16M890IL32-0C Datasheet, PDF (28/63 Pages) Exar Corporation – UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG
A2-A0 NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
000
RHR
RD Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
000
THR
WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX RX Data _{LCR[7] = 0}
CTS# RTS# Xoff Int. Sleep ^{Stat. Int. Stat. Empty Int.}
Int.
Int. Enable Mode ^{Enable Int.}
Int Enable
Enable Enable
Enable
Enable Enable
010
010
ISR
FCR
RD FIFOs FIFOs
0/
0/
INT
INT INT
INT
Enabled Enabled _RTS
Xoff
CTS _Interrupt
Interrupt
Source
Bit-3
Source Source Source _{LCR[7] = 0}
Bit-2 Bit-1 Bit-0 _{if EFR[4]=1}
or
WR RXFIFO RXFIFO TXFIFO TXFIFO Wake up TX
RX FIFOs ^{LCR≠0xBF}
Trigger Trigger Trigger Trigger Int Enable FIFO FIFO Enable ^{if EFR[4]=0}
Reset Reset
011
LCR RD/WR Divisor Set TX Set
Enable Break _Parity
Even
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
100
MCR
RD/WR
0/
BRG
Pres-
caler
0/
0/
IR Mode XonAny
ENable
Internal
Lopback
Enable
INT Out-
put
Enable
(OP2#)
OP1#/ RTS#
GPIO ^Output
Control
Select
DTR#
Output
Control
101
LSR
RD RX FIFO THR & THR RX Break RX Fram- RX
RX RX Data
Global TSR Empty
ing Error Parity Over- Ready
Error Empty
Error run
Error
101
SHR
WR RS-485 RS-485 RS-485 RS-485 RS-485 RS-485 RS-485 RS-485
Setup Setup Setup Setup Delay Delay Delay Delay
Bit-3 Bit-2 Bit-1
Bit-0
Bit-3/ Bit-2/ Bit-1/ Bit-0/ ^{LCR≠0xBF}
Hystere- Hyster- Hyster- Hystere-
sis
esis esis
sis
Bit-3 Bit-2 Bit-1 Bit-0
110
MSR
RD CD#
RI# DSR# CTS#
Input Input Input Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
110
SFR
WR
TX Enable Disable Disable Fast GPIO GPIO GPIO
9-bit
9-bit
RX
TX
mode
IR
INT [15:8]/ Access
Enable [7:0]
Select
111
SPR RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
Bit-2 Bit-1
Bit-0
LCR≠0xBF
FCTR[6]=0
SFR[0]=0
1 1 1 GPIOLVL RD/WR Bit-15/ Bit-14/ Bit-13/ Bit-12/
Bit-7 ^{Bit-6 Bit-5}
Bit-4
Bit-11/ Bit-10/ Bit-9/
Bit-3 Bit-2 Bit-1
Bit-8/
Bit-0
LCR≠0xBF
FCTR[6]=0
SFR[0]=1
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