XR16M890IL32-0C Datasheet, PDF (42/63 Pages) Exar Corporation – UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS Flow Control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The
CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
3.11 Special Function Register (SFR) - Write Only
This register provides access to some of the advanced features of XR16M890. This register can only be
written to if EFR[4] = 1.
SFR[0]: Enable GPIO Registers (Requires EFR[4] = 1)
• Logic 0 = GPIO control and status registers are not enabled.
• Logic 1 = GPIOLVL register is accessible at SPR register location. GPIOINT, GPIO3T, GPIOINV, GPIOSEL
registers are accessible at XON1, XON2, XOFF1, and XOFF2 register locations.
SFR[1]: GPIO[15:8] or GPIO[7:0] Select (Requires EFR[4] = 1)
• Logic 0 = GPIOLVL, GPIOINT, GPIO3T, GPIOINV and GPIOSEL registers will control and report the status
of GPIO[7:0].
• Logic 1 = GPIOLVL, GPIOINT, GPIO3T, GPIOINV and GPIOSEL registers will control and report the status
of GPIO[15:8].
SFR[2]: GPIO Interrupt Enable (Requires EFR[4] = 1)
• Logic 0 = GPIO interrupt is disabled.
• Logic 1 = GPIO interrupt is enabled. GPIOs that have been configured as inputs can generate GPIO
interrupts if the bit is enabled in the GPIOINT register. The polarity of the GPIO interrupt is selected via the
GPIOINV register.
SFR[3]: Enable/Disable fast IR mode (Requires EFR[4] = 1)
The M890 supports the new fast IR transmission with data rate up to 1.152 Mbps.
• Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps (default).
• Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps. For more IR mode information, please
See ”Section 1.19, Infrared Mode” on page 24.
SFR[4]: Enable/Disable Transmitter (Requires EFR[4] = 1)
• Logic 0 = Enable Transmitter (default).
• Logic 1 = Disable Transmitter.
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