XR16L580 Datasheet, PDF (9/47 Pages) Exar Corporation – SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

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REV. 1.2.0
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
E xte rn a l C lo ck
vcc
gnd
VCC
R1
2K
XTAL1
XTAL2
For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at
http://www.exar.com.
2.9 Programmable Baud Rate Generator
The L580 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit (bit-7) in the MCR register. This bit selects the prescaler to divide the input crystal or external clock
by a factor of 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by
a programmable divisor (via DLL and DLM registers) between 1 and (2¹⁶ -1) to obtain a 16X sampling rate
clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver
for data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon
power up.
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
XTAL1
XTAL2
C rysta l
Osc/
Buffer
P re s c a le r
Divide by 1
P re s c a le r
Divide by 4
DLL and DLM
R e g is te rs
M CR Bit-7=0
(default)
Baud Rate
G e n e ra to r
Logic
M CR Bit-7=1
16X
Sam pling
Rate Clock to
Transm itter
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 3 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. When using a non-standard data rate crystal or external clock, the
divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
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