XR16L580 Datasheet, PDF (6/47 Pages) Exar Corporation – SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
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REV. 1.2.0
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L580 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 3.
FIGURE 3. XR16L580 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CS#
UART_INT
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
R/W#
UART_CS#
UART_IRQ#
UART_RESET#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
CS#
INT
RESET
VCC
16/68#
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
RI#
PwrSave
GND
VCC
Serial Interface of
RS-232 or RS-422
Intel Data Bus Interconnections
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
VCC IOR#
IOW#
CS#
INT
RESET
VCC
PwrSave
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
RI#
16/68#
GND
VCC
Serial Interface of
RS-232 or RS-422
Motorola Data Bus Interconnections
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