XR16L580 Datasheet, PDF (3/47 Pages) Exar Corporation – SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

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REV. 1.2.0
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
PIN DESCRIPTIONS
Pin Descriptions
NAME
32-QFN
PIN#
48-TQFP
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
17
26
A1
18
27
A0
19
28
D7
5
4
D6
4
3
D5
3
2
D4
1
47
D3
32
46
D2
31
45
D1
30
44
D0
29
43
IOR#
14
19
(NC)
IOW#
12
16
(R/W#)
CS#
8
11
INT
20
30
(IRQ#)
I _{Address data lines [2:0]. These 3 address lines select one of the internal regis-}
ters in UART channel A/B during a data bus transaction.
I/O _{Data bus lines [7:0] (bidirectional).}
I _{When 16/68# pin is at logic 1, the Intel bus interface is selected and this input}
becomes read strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed by the address
lines [A2:A0], puts the data byte on the data bus to allow the host processor to
read it on the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this
input is not used.
I _{When 16/68# pin is at logic 1, it selects Intel bus interface and this input}
becomes write strobe (active low). The falling edge instigates the internal write
cycle and the rising edge transfers the data byte on the data bus to an internal
register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this
input becomes read (logic 1) and write (logic 0) signal.
I _{This input is chip select (active low) to enable the device.}
O _{When 16/68# pin is at logic 1 for Intel bus interface, this output become the active}
(OD) high device interrupt output. The output state is defined by the user through the
software setting of MCR[3]. INT is set to the active mode when MCR[3] is set to a
logic 1. INT is set to the three state mode when MCR[3] is set to a logic 0. See
MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes the
active low device interrupt output (open drain). An external pull-up resistor is
required for proper operation.
MODEM OR SERIAL I/O INTERFACE
TX
7
8
O _{UART Transmit Data or infrared encoder data. Standard transmit and receive}
interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic
1 during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for
the Infrared encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
RX
6
7
I _{UART Receive Data or infrared receive data. Normal receive data input must idle}
at logic 1 condition. The infrared receiver idles at logic 0.
3