XRS10L240 Datasheet, PDF (8/38 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR

EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
REV. 1.05
3.0 FUNCTIONAL DESCRIPTION
A top-level view of the XRS10L240 is shown in Figure 3 outlining the interfaces to the device and the required
support components. The data path can be seen at the top of the device. This includes the two output transmit
and input receive paths at the top left, providing the upstream interface to the host, and the four output transmit
and input receive paths at the top right, providing the downstream interface to the target devices. The clocking,
control, and configuration interfaces are shown below the dotted line.
FIGURE 3. XRS10L240 INTERFACES
Serial ATA Upstream
Interface to HBAs
SIT_P/N[1:0]
SIR_P/N[1:0]
SOT_P/N[3:0]
SOR_P/N[3:0]
Serial ATA Downstream
Interface to Devices
DRACT[3:0] CMU_REF_P/N
Control and
Status
Interface
HBACT
PS_SIDEBAND_B
PORTSEL
RESETB
XOD
XOG
PWRDNB
TCK
Configuration
Interface
MDC
MDIO
TDI
TDO
TMS
VDDA
RBIAS
TRST
Calibration Resistor
49.9 Ω ± 0.5%
Reference Clock
Crystal Oscillator I/O
JTAG
Interface
The XRS10L240 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This
common building block provides a uniform implementation with common characteristics and a common
register map, but provides a functional implementation of independent PHY blocks. Digital logic
implementations of Serial ATA link layer blocks along with port selector and port multiplier logic provide the
remainder of the data path within the XRS10L240. In addition, management and control interfaces including an
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