XRS10L240 Datasheet, PDF (34/38 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR

EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
REV. 1.05
SError register SCR(1) -
The Serial ATA interface Error register - SError - is a 32-bit register that conveys supplemental Interface error
information to complement the error information available in the Shadow Register Block Error register. The
register represents all the detected errors accumulated since the last time the SError register was cleared
(whether recovered by the interface of not). Set bits in the error register are explicitly cleared by a write
operation to the SError register, or a reset operation. The value written to clear set error bits shall have 1’s
encoded in the bit positions corresponding to the bits that are to be cleared. Host software should clear the
Interface SError register at appropriate checkpoints in order to best isolate error conditions and the commands
they impact.
Bits [31:16] DIAG
The DIAG field contains diagnostic error information for use by diagnostic software in validating correct
operation or isolating failure modes. The field is bit significant as defined in the following figure.
DIAG R R R R A X
F
T S H C D BW
I
N
A
Port Selector presence detected: This bit is set to one when COMWAKE is received while the host is
in state HP2: HR_AwaitCOMINIT. On power-up reset this bit is cleared to zero. The bit is cleared to zero when
the host writes a one to this bit location.
B
10b to 8b Decode error: When set to a one, this bit indicates that one or more 10b to 8b decoding
errors occurred since the bit was last cleared to zero.
C
CRC Error: When set to one, this bit indicates that one or more CRC errors occurred with the Link
layer since the bit was last cleared to zero.
D
Disparity Error: When set to one, this bit indicates that incorrect disparity was detected one or more
times since the last time the bit was cleared to zero.
F
Unrecognized FIS type: When set to one, this bit indicates that since the bit was last cleared one or
more FISes were received by the Transport layer with good CRC, but had atype field that was not recognized.
I
Phy Internal Error: When set to one, this bit indicates that the Phy detected some internal error since
the last time this bit was cleared to zero.
N
PHYRDY change: When set to one, this bit indicates that the PHYRDY signal changed state since the
last time this bit was cleared to zero.
H
Handshake error: When set to one, this bit indicates that one or more R_ERRPhandshake response
was received in response to frame transmission. Such errors may be the result of a CRC error detected by the
recipient, a disparity or 10b/8b decoding error, or other error condition leading to a negative handshake on a
transmitted frame.
R
Reserved bit for future use: Shall be cleared to zero.
S
Link Sequence Error: When set to one, this bit indicates that one or more Link state machine error
conditions was encountered since the last time this bit was cleared to zero. The Link layer state machine
defines the conditions under which the link layer detects an erroneous transition.
T
Transport state transition error: When set to one, this bit indicates that an error has occurred in the
transition from one state to another within the Transport layer since the last time this bit was cleared to zero.
W
COMWAKE Detected: When set to one this bit indicates that a COMWAKE signal was detected by the
Phy since the last time this bit was cleared to zero.
X
Exchanged: When set to one this bit indicates that device presence has changed since the last time
this bit was cleared to zero. The means by which the implementation determines that the device presence has
changed is vendor specific. This bit may be set to one anytime a Phy reset initialization sequence occurs as
determined by reception of the COMINIT signal whether in response to a new device being inserted, in
response to a COMRESET having been issued, or in response to power-up.
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