XRS10L240 Datasheet, PDF (5/38 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR

EXSTOR - 1 XRS10L240
REV. 1.05
2.0 PIN DESCRIPTIONS
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
TABLE 1: XRS10L240 PIN DESCRIPTIONS
Pin Name
Pin Number
I/O
DESCRIPTION
DATA INTERFACE
SOTP0/SOTN0
SOTP1/SOTN1
SOTP2/SOTN2
68, 69
57, 56
8, 7
CML
AC
O
Coupled Serial ATA Output Transmitters. These ports communicate
from the XRS10L240 to downstream devices
SOTP3/SOTN3
19, 20
SORP0/SORN0
65, 66
SORP1/SORN1
60, 59
I
SORP2/SORN2
11, 10
Serial ATA Input Receivers. These ports receive signals
from downstream devices
SORP3/SORN3
16, 17
SITP0/SITN0
93, 94
SITP1/SITN1
82, 81
O
Serial ATA Output Transmitters. These ports communicate
from the XRS10L240 to upstream hosts.
SIRP0/SIRN0
90, 91
SIRP1/SIRN1
85, 84
I
Serial ATA Input Receivers. These ports receive signals
from upstream hosts.
CLOCK INTERFACE
CMU_REFP/
46,
CMU_REFN
47
I
CML Reference clock input
AC
Coupled
XOD
43
0
Analog Crystal oscillator output
XOG
44
I
Analog Crystal oscillator input, 1.26V max
MDIO INTERFACE SIGNALS
MDC
3
I
LVCMOS MDIO clock input, +3.3V LVCMOS
MDIO
5
I/O
LVCMOS MDIO data port, +3.3V LVCMOS. Open drain
JTAG Interface Signals
TCK
96
I
LVCMOS JTAG test clock, +3.3V LVCMOS
TDI
100
I
JTAG test data in, +3.3V LVCMOS
TDO
99
O
JTAG test data out, +3.3V LVCMOS. Open drain. If used
to daisy chain JTAG devices, pull up externally using
3.3KOhm resistor.
TMS
97
I
JTAG mode select, +3.3V LVCMOS
TRST
1
I
JTAG test reset, +3.3V LVCMOS. Pull low externally using
3.3KOhm resistor for normal operation of the device.
GENERAL CONTROL AND CONFIGURATION SIGNALS (CMOS)
RBIAS
49
I
Analog Connection point for calibration termination resistor.
RESETB
75
I
LVCMOS Active low reset pin, +3.3V LVCMOS.
5