XRS10L240 Datasheet, PDF (25/38 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR

EXSTOR - 1 XRS10L240
REV. 1.05
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
5.2 Macro Registers
The registers outlined in this section are common to each of the three Serial ATA dual PHY macros as
described in the previous section. As such, each listed register is present in each of the 1, 2, and 3 MDIO
register spaces, and will perform the stated function on the specified Serial ATA lane.
The registers within each dual PHY macro are split into the following sections:
Transmit/Receive lane 0 registers:
Address range 000*****
Transmit/Receive lane 1 registers:
Address range 001*****
PLL registers:
Address range 010*****
Bias generator registers:
Address range 011*****
ADDRESS
HEX
N.0000
N.0020
N.0001
N.0021
TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3)
BIT(S)
NAME
RW
DEFAULT
DESCRPTION
7
Reserved
RW
0 DO NOT MODIFY
6
SATAPCIEXB_G1
RW
0 Tx output swing booster bit (Gen 1)
0 = boost swing by 15%
1 = nominal swing
5:1
Reserved
RW
0001 DO NOT MODIFY
0
SATAPCIEXB_G2
RW
0 Tx output swing booster bit (Gen 2)
0 = boost swing by 15%
1 = nominal swing
7:3
Reserved
RW
00000 DO NOT MODIFY
2:0
Transmit_Eq0[2:0]
RW
Transmit_Eq1[2:0]
011 Transmit preemphasis control
000 = 0% transmit preemphasis
001 = 6.5% transmit preemphasis
010 = 13% transmit preemphasis
011 = 19.5% transmit preemphasis
100 = 26% transmit preemphasis
101 = 32.5% transmit preemphasis
110 = 39% transmit preemphasis
111 = 45.5% transmit preemphasis
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