XR77128 Datasheet, PDF (8/28 Pages) Exar Corporation – Quad Output Digital PWM/PFM

XR77128
Pin No.
Pin Name
13, 14,
15
PSIO0, PSIO1, PSIO2
16
DVDD
17
DGND
18, 24,
29, 35
BST4, BST3, BST2, BST1
19, 25,
30, 36
20, 26,
31, 37
GH4, GH3, GH2, GH1
LX4, LX3, LX2, LX1
21, 27,
32, 38
22, 28,
33, 39
23, 34
GL4, GL3, GL2, GL1
GL_RTN4, GL_RTN3, GL_RTN2,
GL_RTN1
VCCD3-4, VCCD1-2
40
ENABLE
41
VCC
42
BFB
43
V5EXT
44
LDO5
45
PAD
Description
Open drain, these pins can be used to control external power MOSFETs to switch loads on
and off, shedding the load for fine grained power management. They can also be configures as
standard logic outputs or inputs just as any of the GPIOs can be configured, but as open
drains require an external pull-up when configured as outputs.
1.8V supply input for digital circuitry. Connect pin to AVDD. Place a decoupling capacitor close
to the controller IC.
Digital ground pin. This is the logic ground connection, and should be connected to the ground
plane close to the PAD.
High side driver supply pin(s). Connect BST to the external capacitor as shown in the Typical
Application Circuit. The high side driver is connected between the BST pin and LX pin and
delivers the BST pin voltage to the high side FET gate each cycle.
Output pin of the high side gate driver. Connect directly to the gate of an external N-channel
MOSFET.
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the
junction between the two external power MOSFETs and the inductor. These pins are also
used to measure voltage drop across bottom MOSFETs in order to provide output current
information to the control engine.
Output pin of the low side gate driver. Connect directly to the gate of an external N-channel
MOSFET.
Ground connection for the low side gate driver. This should be routed as a signal trace with
GL. Connect to the source of the low side MOSFET.
Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies drivers 1 and
2 and pin 23 supplies drivers 3 and 4. One of the two pins must be connected to the LDO5 pin
to enable two power rails initially. It is recommended that the other VCCD pin be connected to
the output of a 5V switching rail (for improved efficiency or for driving larger external FETs), if
available, otherwise this pin may also be connected to the LDO5 pin. A bypass capacitor
(>1uF) to the system ground is recommended for each VCCD pin with the pin(s) connected to
LDO5 with shortest possible length of etch.
If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset, regis-
ters configuration loaded, etc.). The pin must be held low for the XR77128 to be placed into
shutdown.
Input voltage. Place a decoupling capacitor close to the controller IC. This input is used in
UVLO fault generation.
Input from the 15V output created by the external boost supply. When this pin goes below a
pre-defined threshold, a pulse is created on the low side drive to charge this output back to the
original level. If not used, this pin should be connected to GND.
External 5V that can be provided. If one of the output channels is configured for 5V, then this
voltage can be fed back to this pin for reduced operating current of the chip and improved effi-
ciency.
Output of a 5V LDO. This LDO is used to power the internal Analog Blocks.
This is the die attach paddle, which is exposed on the bottom of the part. Connect externally to
the ground plane.
© 2014 Exar Corporation
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exar.com/XR77128
Rev 1A