XR77128 Datasheet, PDF (20/28 Pages) Exar Corporation – Quad Output Digital PWM/PFM

XR77128
• External Clock-In – enables the controller to lock to an
external clock including one from another XR77128
applied to the GPIO0 pin. There are two ranges of clock
frequencies the controller accepts, selectable by a user.
• External Clock-Out – clock sent out through GPIO1 for
synchronizing with another XR77128 (see the clock out
section for more information).
Fault Handling
There are seven different types of fault handling in
XR77128:
• Under Voltage Lockout (UVLO) monitors voltage sup-
plied to the VCC pin and will cause the controller to
shutdown all channels if the supply drops to critical lev-
els.
• Over Temperature Protection (OTP) monitors tem-
perature of the chip and will cause the controller to shut-
down all channels if temperature rises to critical levels.
• Over Voltage Protection (OVP) monitors regulated volt-
age of a channel and will cause the controller to react in
a user specified way if the regulated voltage surpasses
threshold level.
• Over Current Protection (OCP) monitors current of a
channel and will cause the controller to react in a user
specified way if the current level surpasses threshold
level.
• Start-up Time-out Fault monitors whether a channel
gets into regulation in a user defined time period.
• LDO5 Over Current Protection (LDO5 OCP) monitors
current drawn from the regulator and will cause the con-
troller to be reset if the current exceeds LDO5 limit.
• LDOOUT Over Current Protection (LDOOUT OCP)
monitors current drawn from the regulator and will cause
the controller to shut down the regulator if the current
exceeds LDOOUT limit.
UVLO
Both UVLO warning and fault levels are user programmable
and set at 200mV increments in PA 5.2.
When the warning level is reached the controller will gener-
ate the UVLO_WARNING_EVENT interrupt. In addition,
the host can be informed about the event through HW
Flags (see the Digital I/O section).
When an UVLO fault condition occurs, the XR77128 out-
puts are shut down and the UVLO_FAULT_AC-
TIVE_EVENT interrupt is generated. In addition, the host
can be informed by forwarding the Low VCC signal to any
GPIO/PSIO (see the Digital I/O section). This signal transi-
tions when the UVLO fault occurs. When coming out of the
fault, rising VCC crossing the UVLO fault level will trigger
the UVLO_FAULT_INACTIVE_EVENT interrupt.
Once UVLO condition clears (VCC voltage rises to or above
the user defined UVLO warning level), the Low VCC signal
will transition and the controller will be reset.
OTP
User defined OTP warning, fault and restart levels are set
at 5°C increments in PA 5.2.
When the warning level is reached the controller will gener-
ate the TEMP_WARNING_EVENT interrupt. In addition,
the host can be informed about the event through HW
Flags (see the Digital I/O section).
When an OTP fault condition occurs, the XR77128 outputs
are shutdown and the TEMP_OVER_EVENT interrupt is
generated.
Once temperature reaches a user defined OTP Restart
Threshold level, the TEMP_UNDER_EVENT interrupt will
be generated and the controller will reset.
OVP
A user defined OVP fault level is set in PA 5.2 and is
expressed in percentages of a regulated target voltage.
Resolution is the same as for the target voltage (expressed
in percentages). The OVP minimum and maximum values
are calculated by the following equation where the range for
N is 1 to 63:
OVP (%) = -^N-----^-----L-V--S--t--Ba---r--g(--m-e--t--V-(--V-)----)^-----1---0---⁵
© 2014 Exar Corporation
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