XR77128 Datasheet, PDF (16/28 Pages) Exar Corporation – Quad Output Digital PWM/PFM

XR77128
Under Voltage OVS: If there is an increasing current load
step, the output voltage will drop until the regulator loop
adapts to the new conditions to return the voltage to the
correct level. Depending on where in the switching cycle the
load step happens there can be a delay of up to one switch-
ing cycle before the control loop can respond. With OVS
enabled if output voltage drops below the lower limit of the
window comparator, an immediate GH pulse will be gener-
ated and sent to the driver to increase the output inductor
current toward the new load level without having to wait for
the next cycle to begin. If the output voltage is still below the
lower limit of the window comparator at the beginning of the
next cycle, OVS will work in conjunction with the PID to
insert additional GH pulses to quickly return the output volt-
age back within its regulation band. The result of this sys-
tem is transient response capabilities on par or exceeding
those of a constant on-time control loop.
Over Voltage OVS: When there is a step load current
decrease, the output voltage will increase (bump up) as the
excess inductor current that is no longer used by the load,
flows into the output capacitors causing the output voltage
to rise. The voltage will continue to rise until the inductor
current decreases to the new load current level. With OVS
enabled, if the output voltage exceeds the high limit of the
window comparator, a blanking pulse is generated to trun-
cate the GH signal. This causes inductor current to immedi-
ately begin decreasing to the new load level. The GH signal
will continue to be blanked until the output voltage falls
below the high limit of the window comparator. Again, since
the output voltage is sampled at four times the switching
frequency, overshoot will be decreased and the time
required to get back into the regulation band is also
decreased.
OVS can be used in conjunction with both the PWM and
PFM operating modes. When it is activated it can notice-
ably decrease output voltage excursions when transitioning
between PWM and PFM modes.
performance and minimize noise coupling to the 5V LDO
supply.
The driver outputs should be connected directly to their cor-
responding output switching FETs with the Lx output con-
nected to the drain of the synchronous FET for the best
current monitoring accuracy.
See ANP-32 “Practical Layout Guidelines for PowerXR
Designs”
LDOs
The XR77128 has two internal Low Drop Out (LDO) linear
regulators that generate 5.0V (LDO5) and configurable volt-
age (LDOOUT) for both internal and external use. XR77128
can be programmed to four LDOOUT output voltage set-
tings, 3.3V, 2.8V, 2.5V and 1.8V. Additionally, XR77128 has
a 1.8V regulator that supplies power for the XR77128 inter-
nal circuits. LDO5 is the main power input to the device and
is supplied by an external 5.5V to 25V (VCC) supply. The
output of LDO5 should be bypassed by a good quality
4.7uF or larger capacitor connected between the pin and
ground close to the device. The 5V output is used by the
XR77128 as a standby power supply and is also used to
power the LDOOUT and 1.8V linear regulators inside the
chip, and can also supply power to the 5V gate drivers. The
total output current that the 5V LDO can provide is 130mA.
The XR77128 consumes approximately 20mA and the rest
is shared between LDOOUT and the gate drive currents.
The LDOOUT output available on the LDOOUT pin is solely
for customer use and is not used internally. This supply is
turned on or off by the configuration registers. Again a good
bypass capacitor should be used.
The AVDD pin is the 1.8V regulator output and needs to be
connected externally to the DVDD pin on the device. A
good quality capacitor should be connected between this
pin and ground close to the package.
Internal Drivers
The internal high and low gate drivers use totem pole FETs
for high drive capability. They are powered by two external
5V power pins (VCCD1-2) and (VCCD3-4). VCCD1-2 pow-
ers the drivers for channels 1 and 2 while VCCD3-4 powers
channels 3 and 4. The drivers can be powered by the inter-
nal 5V LDO by connecting their power pins to the LDO5
output through an RC filter to avoid conducted noise back
into the analog circuitry.
To minimize power dissipation in the 5V LDO, it is recom-
mended to power the drivers from an external 5V power
source either directly or by using the V5EXT input. Good
quality 1uF to 4.7uF capacitors should be connected
directly between the power pins to ground to optimize driver
© 2014 Exar Corporation
16 / 28
exar.com/XR77128
Rev 1A