English
Language : 

XR77128 Datasheet, PDF (17/28 Pages) Exar Corporation – Quad Output Digital PWM/PFM
Clocks and Timing
XR77128
Figure 19: XR77128 Timing Block Diagram
Figure 19 shows a simplified block diagram of the XR77128
timings. Again, please note that the function blocks and sig-
nal names used are chosen for ease of understanding and
do not necessarily reflect the actual device design.
The system timing is generated by a 103MHz internal sys-
tem clock (Sys_Clk). There are two ways that the 103 MHz
system clock can be generated. These include an internal
oscillator and a Phase Locked Loop (PLL) that is synchro-
nized to an external clock input. The basic timing architec-
ture is to divide the Sys_Clk down to create a fundamental
switching frequency (Fsw_Fund) for all the output channels
that is settable from 105kHz to 306kHz. The switching fre-
quency for a channel (Fsw_CHx) can then be selected as 1
time, 2 times or 4 times the fundamental switching fre-
quency.
To set the base frequency for the output channels, an
“Fsw_Set” value representing the base frequency shown in
Table 1 is entered into the switching frequency configuration
register. Note that Fsw_Set value is basically equal to the
Sys_Clk divided by the base frequency. The system timing
is then created by dividing down Sys_Clk to produce a base
frequency clock, 2X and 4X times the base frequency
clocks, and sequencing timing to position the output chan-
nels relative to each other. Each output channel then has
its own frequency multiplier register that is used to select its
final output switching frequency.
Table 1 shows the available channel switching frequencies
for the XR77128 device. In practice the PowerArchitect™
5.2 (PA 5.2) design tool handles all the details and the user
only has to enter the fundamental switching frequency and
the 1x, 2x, 4x frequency multiplier for each channel.
If an external clock is used, the frequencies in this table will
shift according to percentage of frequency deviation
between the clock supplied and nominal value for a given
locking range.
© 2014 Exar Corporation
17 / 28
exar.com/XR77128
Rev 1A