XR77128 Datasheet, PDF (14/28 Pages) Exar Corporation – Quad Output Digital PWM/PFM

Regulation Loops
XR77128
Figure 17: Regulation Loops
Figure 17 shows a simplified functional block diagram of the
regulation loops for one output channel of the XR77128.
There are four separate parallel control loops: Pulse Width
Modulation (PWM), Pulse Frequency Modulation (PFM),
Ultrasonic, and Over Sampling (OVS). Each of these loops
is fed by the Analog Front End (AFE) as shown at the left of
the diagram. The AFE consist of an input voltage scaler, a
programmable Voltage Reference (Vref) DAC, Error Ampli-
fier, and a window comparator. Some of the functional
blocks are common and shared by each channel by means
of a multiplexer.
PWM Loop
The PWM loop operates in Voltage Control Mode (VCM)
with optional Vin feed forward based on the voltage at the
VCC pin. The reference voltage (Vref) for the error amp is
created by a 0.15V to 1.6V DAC that has a 12.5mV resolu-
tion. In order to provide a 0.6V to 5.5V output voltage range,
an input scaler is used to reduce feedback voltages for
higher output voltages to bring them within the 0.15V to
1.6V control range. So for output voltages up to 1.6V (low
range), the scaler has a gain of 1. For output voltages from
1.6V to 3.2V (mid range) the scalar gain is 1/2, and for volt-
ages greater than 3.2V (high range) the gain is 1/4. This
results in the low range having a reference voltage resolu-
tion of 12.5mV, the mid range having a resolution of 25mV,
and the high range having a resolution of 50mV. The error
amp has a gain of 4 and compares the output voltage of the
scaler to Vref to create an error voltage on its output. This is
converted to a digital error term by the AFE ADC and is
stored in the error register. The error register has a fine
adjust function that can be used to improve the output volt-
age set point resolution by a factor of 5 resulting in a low
range resolution of 2.5mV, a mid range resolution of 5mV
and a high range resolution of 10mV. The output of the error
register is then used by the Proportional Integral Derivative
(PID) controller to manage the loop dynamics.
The XR77128 PID is a 17-bit five-coefficient control engine
that calculates the required duty cycle under the various
operating conditions and feeds it to the digital Pulse Width
Modulator (PWM). Besides the normal coefficients, the PID
also uses the VCC voltage to provide a feed forward func-
tion.
The XR77128 digital PWM includes a special delay timing
loop that provides a timing resolution that is 16 times the
master oscillator frequency (103MHz) for a timing resolution
of 607ps for both the driver pulse width and dead time
delays. The PWM produces the Gate High (GH) and Gate
Low (GL) signals to the driver. The maximum and minimum
on times and dead time delays are programmable by con-
figuration resisters.
To provide current information, the output inductor current
is measured by a differential amplifier that reads the voltage
drop across the RDSON of the synchronous FET during its
on time. There are two selectable ranges, a low range with
a gain of 8 for a -120mV to +20mV voltage range, and a
high range with a gain of 4 for -280mV to +40mV voltage
range. The optimum range to use will depend on the maxi-
mum output current and the RDSON of the synchronous
FET. The measured voltage drop is then converted to a dig-
ital value by the current ADC block. The resulting current
© 2014 Exar Corporation
14 / 28
exar.com/XR77128
Rev 1A