XR77128 Datasheet, PDF (25/28 Pages) Exar Corporation – Quad Output Digital PWM/PFM

XR77128
to the interface schematics shown below. The GH pin is not
used in this mode and needs to be left floating.
Connecting the LX pin to the switch node and the GL_RTN
pin to the PGND (synchronous MOSFET source) of the
DrMOS device allows current monitoring, Over-Current
Warning and Over-Current Fault operation. The boost cap
must be connected between the LX and BST pins to ensure
proper biasing of the internal circuitry.
If current monitoring is not needed, the LX pin should be
grounded. The boost cap will be connected between the
BST and LX pins.
The PWM output is a 5V signal and does not support tri-
state. Only CCM operation is recommended. When setting
the Active Shutdown Threshold level, using a low value
(100mV for instance) to discharge the output capacitors
and avoid a possibility of a negative ring on the output
during shut down is recommended.
RAM with a chip that already contains a valid configuration
in FLASH NVM, the first step will be to invalidate the FLASH
configuration. The device will be reset to clear the prior
RAM content and then the new run time configuration gets
loaded. PA 5.2 will indicate that it successfully downloaded
the configuration to run time registers after which the “Chip
Ready” indicator will be asserted by PA 5.2 acting as a
host.
If the configuration changes I²C address, the device will
respond to the new address at this point.
For users that wish to create their own downloading proce-
dure, they can refer to ANP-39.
Programming XR77128
Once the design has been tested and verified its configura-
tion can permanently be saved into FLASH NVM.
XR77128 is a Flash based device which means its configu-
ration can be programmed into Flash NVM and re-pro-
grammed a number of times.
Programming of FLASH NVM is done through PA 5.2.
Downloading Configuration to XR77128
A key benefit of Exar’s programmable power technology is
the ability to easily update the design and chip configura-
tion during development. The best way to do this is to pro-
gram the RAM memory rather than programming the
FLASH NVM.
PA 5.2 provides a RAM download function accessible
through the Dashboard or through the “Tools” menu.
RAM programming requires that there is no valid configura-
tion in the FLASH NVM. A valid configuration is loaded in
the chip if in the Dashboard window, the “Reset Chip” (F8)
button is clicked and after a short delay the “Chip Ready”
indicates “Yes”. When a new configuration is loaded into
By clicking on the Flash button, user will start programming
sequence of the design configuration into the Flash NVM.
After the programming sequence completes, the chip will
© 2014 Exar Corporation
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Rev 1A