XR16M2551 Datasheet, PDF (8/51 Pages) Exar Corporation – HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE

XR16M2551
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.2
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The M2551 data interface supports the Intel compatible types of CPUs and it is compatible
to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data
bus transaction. Each bus cycle is asynchronous using CSA#/CSB#, IOR# and IOW# or CS#, R/W# and A3
inputs. Both UART channels share the same data bus for host operations. A typical data bus interconnection
for Intel and Motorola mode is shown in Figure 3.
FIGURE 3. XR16M2551 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IO R #
IO W #
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
R /W #
UART_CS#
U A R T _IR Q #
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
UART_RESET#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IO R #
IO W #
CSA#
CSB#
INTA
INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
VCC
UART
Channel A
TXA
RXA
DTRA#
RTSA#
CTSA#
DSRA#
CDA#
RIA#
OP2A#
UART
Channel B
TXB
RXB
DTRB#
RTSB#
CTSB#
DSRB#
CDB#
RIB#
OP2B#
RESET
GND
VCC
Serial Interface of
RS-232, RS-422
(no connect)
Serial Interface of
RS-232, RS-422
(no connect)
Intel Data Bus Interconnections
VCC
VCC
(no connect)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSB#
IO R #
IO W #
CSA#
INTA
INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
RESET#
VCC
UART
Channel A
TXA
RXA
DTRA#
RTSA#
CTSA#
DSRA#
CDA#
RIA#
OP2A#
TXB
RXB
DTRB#
UART ^RTSB#
Channel B CTSB#
DSRB#
CDB#
RIB#
OP2B#
GND
1.62 to 3.63 Volt VCC
Serial Interface of
RS-232, RS-422
(no connect)
Serial Interface of
RS-232, RS-422
(no connect)
Motorola Data Bus Interconnections
2.2 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
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