XR16M2551 Datasheet, PDF (7/51 Pages) Exar Corporation – HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE

XR16M2551
REV. 1.0.2
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
1.0 PRODUCT DESCRIPTION
The XR16M2551 (M2551) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver
and Transmitter (UART). Its features set is compatible to the XR16M2550 and XR16V2550 devices but offers
Intel or Motorola data bus interface and PowerSave to isolate the data bus interface during Sleep mode.
Hence, the M2551 adds 3 more inputs: 16/68#, PwrSave and CLKSEL pins. Each UART is independently
controlled by its own set of device configuration registers. The configuration registers set is 16550 UART
compatible for control status and data transfer. Additionally, each UART channel has automatic RTS/CTS
hardware flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and
decoder (IrDA ver 1.0), and programmable fractional baud rate generator with a prescaler of divide by 1 or 4.
The XR16M2551 can operate from 1.62V to 3.63V. The M2551 is fabricated with an advanced CMOS process.
Enhanced Features
The M2551 DUART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The
M2551 is designed to work with low supply voltage and high performance data communication systems, that
require fast data processing time. In addition, the selectable FIFO trigger level interrupt and automatic
hardware/software flow control is uniquely provided for good data throughput performance especially when
operating in a multi-channel system.
Data Bus Interface, Intel or Motorola Type
The M2551 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor
(CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type
of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible
interface instead uses the R/W#, CS# and A3 signals for data bus transactions. Few data bus interface signals
change their functions depending on user’s selection, see pin description for details. The Intel and Motorola
bus interface selection is made through the 16/68# pin.
Data Rate
The M2551 is capable of operation up to 4 Mbps at 3.3V with 16X internal sampling clock rate, 8 Mbps at 3.3V
with 8X sampling clock rate and 16 Mbps at 3.3V with 4X sampling clock rate. The device can operate with an
external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1 pin.
With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for data
rates of up to 3.68 Mbps.
The rich feature set of the M2551 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, programmable TX and RX baud rates, infrared
encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
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