XR16M2551 Datasheet, PDF (51/51 Pages) Exar Corporation – HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE

XR16M2551
REV. 1.0.2
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 25
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 26
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 27
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 27
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 27
TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 28
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 28
TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 29
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 29
TABLE 13: PARITY SELECTION ........................................................................................................................................................ 31
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 31
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 32
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 33
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 34
4.11 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE ....................................... 34
TABLE 14: SAMPLING RATE SELECT ............................................................................................................................................... 34
4.12 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY....................................................................... 35
4.13 DEVICE REVISION REGISTER (DREV) - READ ONLY................................................................................. 35
4.14 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 35
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 35
4.14.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 36
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 37
5.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 38
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 38
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) ............................................... 38
DC ELECTRICAL CHARACTERISTICS............................................................................................................. 38
AC ELECTRICAL CHARACTERISTICS............................................................................................................. 39
FIGURE 13. CLOCK TIMING............................................................................................................................................................. 40
FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 41
FIGURE 15. 16 MODE (INTEL) DATA BUS READ TIMING ................................................................................................................... 41
FIGURE 16. 16 MODE (INTEL) DATA BUS WRITE TIMING ................................................................................................................. 42
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 42
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 43
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 43
FIGURE 20. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 44
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 44
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 45
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 45
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 46
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm) ............................................................................... 47
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm) .................................................................................. 48
REVISION HISTORY ..................................................................................................................................... 49
TABLE OF CONTENTS ..................................................................................................... I
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