XR82C684CJ-F Datasheet, PDF (71/107 Pages) Exar Corporation – CMOS Quad Channel UART(QUART)

XR82C684
Bit 7
! $+
L:
 L H%
Bit 6
! $+
L:
 L H%
Bit 5
! $+
L:
 L H%
Bit 4
! $+0
L:
 L H%
Bit 3
$+
L< 3
 L ;(,
Bit 2
$+
L< 3
 L ;(,
Bit 1
$+
L< 3
 L ;(,
Bit 0
$+0
L< 3
 L ;(,
Table 19. Input Port Configuration Register 2 - IPCR2
$       /$  + 
 , * 1 ( #  %    *  3( ,
 E(    (      3 ( * 
 
  -  
   ( * % *    
% 
%   3 Please note that the applicable bits, within each of the ACR registers, are shaded.
Bit 7
)2 
'
 L 
 L 
Bit 6
Bit 5
Bit 4

 -( D      '
 Table 4
Bit 3
! $+4
$ 
 L 
 L :
Bit 2
! $+
$ 
 L 
 L :
Table 20. ACR1- Auxiliary Control Register 1
Bit 1
! $+
$ 
 L 
 L :
Bit 0
! $+
$ 
 L 
 L :
Bit 7
)2 
'
 L 
 L 
Bit 6
Bit 5
Bit 4

 -( D      '
 Table 4
Bit 3
! $+
$ 
 L 
 L :
Bit 2
! $+
$ 
 L 
 L :
Bit 1
! $+
$ 
 L 
 L :
Bit 0
! $+0
$ 
 L 
 L :
Table 21. ACR2 - Auxiliary Control Register 2
 ( , $PBQ  -  $PBQ
Note: This “two-tiered” interrupt enabling/disabling
approach, for the “Input Change of State” interrupt allows
tremendous flexibility for the user. Setting or clearing the
bits in ACR1[3:0] and/or ACR2[3:0] allows the user to
specify exactly which Input Port pins to be enabled (or
disabled) for generating the “Input Port Change of State”
interrupt. Setting or clearing IMR1[7] and/or IMR2[7]
allows the user to “globally” enable or disable this
interrupt.
   ( *   3 $+
% 3( ( (' 3 (' *
  (,  (  ( % "( '   /
 , * 1
   3 ( * ' $+
 ' ( %   %  %
*  % (  ( %  * # 3  ( ,  *  
$+
%# ( % %    /
 , * 1 ( #  

+ 3( ( 7
   (  ( %    ,,
   *(  % *   '  ,( , (  ( 
E.3 44 Pin PLCC Packaged QUARTs
  @@ ( +<

'6,  % '  3( & * 
(    ( %# $+# $+# $+0   $+  * #   &
 ( * '( %    (    (' (
 % (    ( %   
 
   
* '( % *  ' '   5"  ' '6 ( %  
( (   @@ ( +<

'6, ( 
F. OUTPUT PORT
    ' %(%% *  . (   + 
   +  '  % %  ,   % 
 '  % *   (( ,   %% %(, % &
 (&  ,( , *     ,(%% #
)#
# !   # )#
# !   %     
' *(,( ,(%%# +
   +
 E  %
  %% %(, %    +  ( %  
 
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