XR82C684CJ-F Datasheet, PDF (24/107 Pages) Exar Corporation – CMOS Quad Channel UART(QUART)

XR82C684
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Note: If this bit is configured to reflect the FFULLC
indicator, this bit will not be set (nor will produce an
interrupt request) if one or two characters are still
remaining in RHRC, following data reception. Hence, it is
possible that the last two characters in a string of data
(being received) could be lost due to this phenomenon.
Therefore, the user is advised to read RHRC until empty.
ISR2[0]: Channel C Transmitter Ready
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C.2 Interrupt Mask Registers (IMR1 and IMR2)
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IMR1 Bit Format
Bit 7
Input Port
Change
 L **
 L 
Bit 6
Delta Break
B
 L **
 L 
Bit 5
RXRDY/
FFULLB
 L **
 L 
Bit 4
TXRDYB
 L **
 L 
Bit 3
Counter
Ready
 L **
 L 
Bit 2
Delta Break
A
 L **
 L 
Bit 1
RXRDY/
FFULLA
 L **
 L 
Bit 0
TXRDYA
 L **
 L 
IMR2 Bit Format
Bit 7
Input Port
Change
 L **
 L 
Bit 6
Delta Break
D
 L **
 L 
Bit 5
RXRDY/
FFULLD
 L **
 L 
Bit 4
TXRDY D
 L **
 L 
Bit 3
Counter
Ready
 L **
 L 
Bit 2
Delta Break
C
 L **
 L 
Bit 1
RXRDY/
FFULLC
 L **
 L 
Bit 0
TXRDYC
 L **
 L 
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Please note that the IMRs are Write Only Registers, and
can therefore not be read by the processor.
C.3 Masked Interrupt Status Register (MISR1 and
MISR2)
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