XR82C684CJ-F Datasheet, PDF (45/107 Pages) Exar Corporation – CMOS Quad Channel UART(QUART)

XR82C684
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Figure 19. A Diagram of Numerous QUARTs configured in an Interrupt Daisy Chain (for Z-Mode Operation)
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IEI - Interrupt Enable Input
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Note: those interrupts which have been masked out by
the IMR are still disabled. However, if this input is at a
logic “low”, then all interrupts (whether masked or
unmasked) are disabled. Hence, IEI can act to globally
disable all QUART interrupt requests.
IEO - Interrupt Enable Output
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Note: Once the IEO pin has toggled “low”, and the CPU
has acknowledged the interrupt request and has
completed the interrupt service routine, the IEO pin will
remain “low” until the user invokes the “RESET IUS”
command (see Table 2). Therefore, if the QUART is
going to operate in the Z-Mode, the user must include the
“RESET IUS” Command at the very end of the QUART
interrupt service routine.
System Level Application of the IEI and IEO pins
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