XRT94L33_07 Datasheet, PDF (611/862 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - ATM REGISTERS

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XRT94L33
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Change in PLM-
P Condition
Interrupt Status
New C2 Byte
Interrupt Status
Change in C2
Byte Unstable
Condition
Interrupt Status
Change in RDI-
P Unstable
Condition
Interrupt Status
RUR
RUR
RUR
RUR
out the state of Bit 5 (UNEQ-P Defect Declared) within the
“Receive STS-1 Path – SONET Receive POH Status – Byte 0”
Register (Address Location= 0xN187).
Change in PLM-P (Path – Payload Mismatch) Condition Interrupt
Status:
This RESET-upon-READ bit indicates whether or not the “Change in PLM-P
Condition” interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will
generate an interrupt in response to either of the following conditions.
• When the Receive STS-1 POH Processor block declares the “PLM-P”
Condition.
• When the Receive STS-1 POH Processor block clears the “PLM-P”
Condition.
0 – Indicates that the “Change in PLM-P Condition” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Change in PLM-P Condition” Interrupt has occurred
since the last read of this register.
New C2 Byte Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New C2
Byte” Interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will
generate an interrupt anytime it has accepted a new C2 byte.
0 – Indicates that the “New C2 Byte” Interrupt has NOT occurred since the
last read of this register.
1 – Indicates that the “New C2 Byte” Interrupt has occurred since the last
read of this register.
Change in C2 Byte Unstable Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change in
C2 Byte Unstable Condition” Interrupt has occurred since the last read of
this register.
If this interrupt is enabled , then the Receive STS-1 POH Processor block
will generate an interrupt in response to either of the following events.
• When the Receive STS-1 POH Processor block declares the “C2 Byte
Unstable” condition.
• When the Receive STS-1 POH Processor block clears the “C2 Byte
Unstable” condition.
0 – Indicates that the “Change in C2 Byte Unstable Condition” Interrupt has
NOT occurred since the last read of this register.
1 – Indicates that the “Change in C2 Byte Unstable Condition” Interrupt has
occurred since the last read of this register.
Note:
The user can determine the current state of “C2 Byte Unstable
Condition” by reading out the state of Bit 6 (C2 Byte Unstable
Condition) within the “Receive STS-1 Path – SONET Receive
POH Status – Byte 0” Register (Address Location= 0xN187).
Change in RDI-P Unstable Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change in
RDI-P Unstable Condition” interrupt has occurred since the last read of this
register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will
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