XRT94L33_07 Datasheet, PDF (589/862 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - ATM REGISTERS

Rev222...000...000
XRT94L33
333---CCCHHHAAANNNNNNEEELLL DDDSSS333///EEE333///SSSTTTSSS---111 TTTOOO SSSTTTSSS---333///SSSTTTMMM---111 MMMAAAPPPPPPEEERRR ––– AAATTTMMM RRREEEGGGIIISSSTTTEEERRRSSS
Table 522: Receive STS-1 Transport – Receive SF Burst Error Tolerance – Byte 1 (Address Location=
0xN156)
BIT 7
R/W
1
BIT 6
R/W
1
BIT 5
R/W
1
BIT 4
BIT 3
SF_BURST_TOLERANCE[15:8]
R/W
R/W
1
1
BIT 2
R/W
1
BIT 1
R/W
1
BIT 0
R/W
1
BIT NUMBER
NAME
7-0
SF_BURST_TOLERANCE[15:8]
TYPE
R/W
DESCRIPTION
SF_BURST_TOLERANCE – MSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-1 Transport – SF BURST Tolerance – Byte 0”
registers permit the user to specify the maximum number of
B2 bit errors that the corresponding Receive STS-1 TOH
Processor block can accumulate during a single Sub-Interval
period (e.g., an STS-1 frame period), when determining
whether or not to declare an SF (Signal Failure) condition.
Note:
The purpose of this feature is to permit the user to
provide some level of B2 error burst filtering, when
the Receive STS-1 TOH Processor block is
accumulating B2 byte errors in order to declare the
SF defect condition. The user can implement this
feature in order to configure the Receive STS-1
TOH Processor block to detect B2 bit errors in
multiple “Sub-Interval” periods before it will declare
the SF defect condition.
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