XRT94L33_07 Datasheet, PDF (260/862 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - ATM REGISTERS

XRT94L33
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Rev222...000...000
BIT NUMBER
NAME
7-0
SD_CLEAR_MONITOR_WINDOW[15:8]
TYPE
R/W
DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL – Bits 15
through 8:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD Clear
Monitor Interval – Byte 2 and Byte 0” registers permit
the user to specify the number of STS-3 Frame
periods that will constitute a CLEAR Sub-Interval for
SD (Signal Degrade).
When the Redundant Receive STS-3 TOH
Processor block is checking for clearing the SD
defect, it will accumulate B2 errors for a total of 8
SET Sub-Interval periods. If the number of
accumulated B2 errors is less than that of
programmed into the “Redundant Receive STS-3
Transport SD Clear Threshold” register, then the SD
defect will be cleared.
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