XR17C154_05 Datasheet, PDF (61/62 Pages) Exar Corporation – 5V PCI BUS QUAD UART

xr
REV. 1.3.2
TABLE OF CONTENTS
XR17C154
5V PCI BUS QUAD UART
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS ............................................................................................................................................... 1
FEATURES ..................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1
FIGURE 2. PIN OUT OF THE DEVICE.................................................................................................................................................. 2
ORDERING INFORMATION ................................................................................................................................ 2
PIN DESCRIPTIONS ......................................................................................................... 3
FUNCTIONAL DESCRIPTION ........................................................................................... 6
PCI Local Bus Interface............................................................................................................................................... 6
1.0 XR17C154 REGISTERS ........................................................................................................................ 7
FIGURE 3. THE XR17C154 REGISTER SETS .................................................................................................................................... 7
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................ 7
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ......................................................................................................... 8
1.2 DEVICE CONFIGURATION REGISTER SET .................................................................................................. 9
TABLE 2: XR17C154 DEVICE CONFIGURATION REGISTERS............................................................................................................. 10
TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ................................................................................... 12
TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT .............................................................................. 12
1.2.1 THE INTERRUPT STATUS REGISTER ..................................................................................................................... 13
FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3 .................................................................................. 14
TABLE 5: UART CHANNEL [3:0] INTERRUPT SOURCE ENCODING..................................................................................................... 14
TABLE 6: UART CHANNEL [3:0] INTERRUPT CLEARING ................................................................................................................... 14
1.2.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-
00-00) ............................................................................................................................................................................. 15
FIGURE 5. TIMER/COUNTER CIRCUIT............................................................................................................................................... 15
TABLE 7: TIMER CONTROL REGISTERS ...................................................................................................................................... 15
1.2.3 8XMODE [7:0] (DEFAULT 0X00)................................................................................................................................ 16
1.2.4 REGA [15:8] RESERVED ........................................................................................................................................... 16
1.2.5 RESET [23:16] (DEFAULT 0X00)............................................................................................................................... 16
1.2.6 SLEEP [31:24]................................................................................................................................. (DEFAULT 0X00) 17
1.2.7 DEVICE IDENTIFICATION AND REVISION............................................................................................................... 17
1.2.8 REGB REGISTER ....................................................................................................................................................... 18
1.2.9 MULTI-PURPOSE INPUTS AND OUTPUTS .............................................................................................................. 18
1.2.10 MPIO REGISTER ...................................................................................................................................................... 18
FIGURE 6. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT........................................................................................................... 19
2.0 CRYSTAL OSCILLATOR / BUFFER ................................................................................................... 21
FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 21
FIGURE 8. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 21
3.0 TRANSMIT AND RECEIVE DATA ...................................................................................................... 22
3.1 DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS ............................................... 22
3.1.1 NORMAL RX FIFO DATA UNLOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700........................................ 22
3.1.2 SPECIAL RX FIFO DATA UNLOADING AT LOCATIONS 0X180, 0X380, 0X580, AND 0X780 .............................. 23
3.1.3 TX FIFO DATA LOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700 ............................................................. 23
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN
8-BIT FORMAT .............................................................................................................................................. 24
TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE ............................................................ 24
4.0 UART .................................................................................................................................................... 25
4.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 25
FIGURE 9. BAUD RATE GENERATOR ............................................................................................................................................... 25
TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING.......................................... 26
4.2 TRANSMITTER ............................................................................................................................................... 26
4.2.1 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 26
4.2.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 26
FIGURE 10. TRANSMITTER OPERATION IN NON-FIFO MODE ............................................................................................................ 27
4.2.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 27
4.2.4 AUTO RS485 OPERATION ........................................................................................................................................ 27
FIGURE 11. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................... 27
4.3 RECEIVER ...................................................................................................................................................... 28
4.3.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ........................................................................................... 28
4.3.2 RECEIVER OPERATION IN NON-FIFO MODE ........................................................................................................ 28
FIGURE 12. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................. 28
I