XR17C154_05 Datasheet, PDF (6/62 Pages) Exar Corporation – 5V PCI BUS QUAD UART

XR17C154
5V PCI BUS QUAD UART
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REV. 1.3.2
FUNCTIONAL DESCRIPTION
The XR17C154 (154) integrates the functions of 4 enhanced 16550 UARTs with the PCI Local Bus interface
and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/counter, 8
multi-purpose inputs/outputs, and an on-chip oscillator. The PCI local bus is a synchronous timing bus where
all bus transactions are associated to the bus clock of up to 33.34MHz. The 154 supports 32-bit wide read and
write data transfer operations including data burst mode through the PCI Local Bus interface. Read and write
data operations may be in byte, word or double-word (DWORD) format. A single 32-bit interrupt status register
provides interrupts status for all 4 UARTs, timer/counter, multipurpose inputs/outputs, and a special sleep wake
up indicator. There are three sets of register in the device. First, the PCI local bus configuration registers for
PCI auto configuration. A set of device configuration registers for overall control, 32-bit wide transmit and re-
ceive data transfer, and monitoring of the 4 UART channels. Lastly, each UART channel has its own 16550
UART compatible configuration register set for individual channel control, status, and byte wide data transfer.
Each UART has 64-byte FIFOs, automatic RTS/CTS or DTR/DSR hardware flow control with hysteresis con-
trol, automatic Xon/Xoff and special character software flow control, programmable transmit and receive FIFO
trigger level, FIFO level counters, infrared encoder and decoder (IrDA ver. 1.0), programmable baud rate gen-
erator with a prescaler of 1X or 4X, and data rate up to 6.25 Mbps at 8X sampling clock. The XR17C154 bus
timing and drive capability meets the PCI local bus specification revision 2.2 for 5 volt operation over the tem-
perature range. For a pin-to-pin compatible part that can operate at 3.3V, see the XR17D154. The XR17C154
is available in a thin 144-pin LQFP (20x20x1.4mm) package in commercial and industrial temperature ranges.
PCI LOCAL BUS INTERFACE
This is the host interface and it meets the PCI Local Bus Specification revision 2.2. The PCI local bus opera-
tions are synchronous meaning each transaction is associated to the bus clock. The XR17C154 can operate
with the bus clock of up to a 33.34MHz. Data transfers operation can be formatted in 8-bit, 16-bit, 24-bit or 32-
bit wide. With 32-bit data operations, it pushes the data transfer rate on the bus up to 132 MByte/sec. This in-
creases the overall system’s communication performance up to 16 times better than the 8-bit ISA bus. See PCI
local bus specification revision 2.2 for bus operation details.
PCI Local Bus Configuration Space Registers
A set of PCI local bus configuration space register is provided. These registers provide the PCI local bus oper-
ating system with the card’s vendor ID, device ID, sub-vendor ID, product model number, and resources and
capabilities. The PCI local bus operating system collects this data from all the cards on the bus during the auto
configuration phase that follows immediately after a power up or system reset/reboot. After it has sorted out all
devices on the bus, it defines and download the operating conditions to the cards. One of the definitions is the
base address loaded into the Base Address Register (BAR) where the card will be operating in the PCI local
bus memory space.
EEPROM Interface
An external 93C46 EEPROM is only used to store the vendor’s ID and model number, and the sub-vendor’s ID
and product model number. This information is only used with the plug-and-play auto configuration of the PCI
local bus. These data provide automatic hardware installation onto the PCI bus. The EEPROM interface con-
sists of 4 signals, EEDI, EEDO, EECS, and EECK. The EEPROM is not needed when auto configuration is not
required in the application. However, If your design requires non-volatile memory for other purpose. It is possi-
ble to store and retrieve data on the EEPROM through a special PCI device configuration register. See applica-
tion note DAN112 for its programming details.
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