XR17C154_05 Datasheet, PDF (10/62 Pages) Exar Corporation – 5V PCI BUS QUAD UART

XR17C154
5V PCI BUS QUAD UART
xr
REV. 1.3.2
TABLE 2: XR17C154 DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS
MEMORY SPACE
READ/WRITE
DATA WIDTH
COMMENT
0x000 - 0x00F
UART channel 0 Regs
(Table 11 &
Table 12)
8/16/24/32 First 8 regs are 16550 compatible
0x010 - 0x07F
Reserved
0x080 - 0x093
DEVICE CONFIG.
REGISTERS
(Table 3)
8/16/24/32
0x094 - 0x0FF Reserved
0x100 - 0x13F
UART 0 – Read FIFO
Read-Only
8/16/24/32 64 bytes of RX FIFO data
0x100 - 0x13F
UART 0 – Write FIFO
Write-Only
8/16/24/32 64 bytes of TX FIFO data
0x140 - 0x17F
Reserved
0x180 - 0x1FF
UART 0 – Read FIFO
with errors
Read-Only
16/32 64 bytes of RX FIFO data + LSR
0x200 - 0x20F
UART channel 1 Regs
0x210 - 0x2FF
0x300 - 0x33F
0x300 - 0x33F
0x340 - 0x37F
0x380 - 0x3FF
Reserved
UART 1 – Read FIFO
UART 1 – Write FIFO
Reserved
UART 1 – Read FIFO
with errors
(Table 11 &
Table 12)
Read-Only
Write-Only
Read-Only
8/16//24/32 First 8 regs are 16550 compatible
8/16/24/32 64 bytes of RX FIFO data
8/16/24/32 64 bytes of TX FIFO data
16/32 64 bytes of RX FIFO data + LSR
0x400 - 0x40F
UART channel 2 Regs
0x410 - 0x4FF
0x500 - 0x53F
0x500 - 0x53F
0x540 - 0x57F
0x580 - 0x5FF
Reserved
UART 2 – Read FIFO
UART 2 – Write FIFO
Reserved
UART 2 – Read FIFO
with errors
(Table 11 &
Table 12)
Read-Only
Write-Only
Read-Only
8/16/24/32 First 8 regs are 16550 compatible
8/16/24/32 64 bytes of RX FIFO data
8/16/24/32 64 bytes of TX FIFO data
16/32 64 bytes of RX FIFO data + LSR
0x600 - 0x60F
UART channel 3 Regs
0x610 - 0x6FF
0x700 - 0x73F
0x700 - 0x73F
Reserved
UART 3 – Read FIFO
UART 3 – Write FIFO
(Table 11 &
Table 12)
Read-Only
Write-Only
8/16/24/32 First 8 regs are 16550 compatible
8/16/24/32 64 bytes of RX FIFO data
8/16/24/32 64 bytes of TX FIFO data
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