XR16M570 Datasheet, PDF (6/52 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

XR16M570
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
REV. 1.0.0
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The M570 data interface supports the Intel compatible types of CPUs. No clock (oscillator
nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS#, IOR#
and IOW# inputs. A typical data bus interconnection for Intel mode is shown in Figure 3.
FIGURE 3. XR16M570 TYPICAL INTEL DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CS#
UART_INT
POWERSAVE
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
CS#
INT
PwrSave
RESET
VCC
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
RI#
GND
Intel Data Bus Interconnections
VCC
Serial Transceivers of
RS-232
RS-485
RS-422
Or Infrared
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