XR16M570 Datasheet, PDF (24/52 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

XR16M570
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
REV. 1.0.0
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX _{LCR[7] = 0}
Stat. Int. Stat. Empty Data
CTS# RTS# Xoff Int. Sleep _{Enable Int.}
Int
Int.
Int.
Int. Enable Mode
Enable Enable
Enable
Enable Enable Enable
010
010
ISR
FCR
RD FIFOs FIFOs
0/
0/
INT
INT INT INT
Enabled Enabled
RTS
CTS
Interrupt
Xoff
Interrupt
Source
Bit-3
Source
Bit-2
Source
Bit-1
Source
Bit-0
LCR[7] = 0
if EFR[4]=1
or
WR RXFIFO RXFIFO TXFIFO TX FIFO Wake up TX
Trigger Trigger Trigger Trigger Int Enable FIFO
RX
FIFO
FIFOs
Enable
LCR≠0xBF
if EFR[4]=0
Reset Reset
011
LCR RD/WR Divisor Set TX Set
Enable Break _Parity
Even
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
100
101
MCR RD/WR
0/
BRG
Pres-
caler
0/
0/
IR Mode XonAny
ENable
Internal
Lopback
Enable
INT Out-
put
Enable
(OP2#)
OP1# RTS# DTR#
Output Output
Control Control
LSR RD RX FIFO THR & THR RX Break RX Fram- RX
RX
RX
Global TSR Empty
ing Error Parity Over- Data
Error Empty
Error run Ready
Error
LCR≠0xBF
110
MSR
RD CD#
RI# DSR# CTS#
Input Input Input Input
WR Fast IR Enable Disable Disable
9-bit
RX
TX
mode
Delta
CD#
0
Delta Delta Delta
RI# DSR# CTS#
0
0
0
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5
111
111
EMSR
FC
WR
Xoff
LSR
interrupt interrupt
mode mode
select select
RD Bit-7 Bit-6
0
Bit-5
Bit-4
0
Bit-4
Bit-3
Invert
RTS in
RS485
mode
Bit-3
Bit-2 Bit-1 Bit-0 LCR≠0xBF
FCTR[6]=0
Send
TX
imme-
diate
Bit-2
FIFO
count
control
bit-1
Bit-1
FIFO
count
control
bit-0
LCR≠0xBF
FCTR[6]=1
Bit-0
24